A parallelised max-log-map model (P-max-log-map) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed mo...
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A parallelised max-log-map model (P-max-log-map) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-log-map algorithm;and therefore facilitates easy implementation.
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