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Maximizing multiprocessor performance with the SUIF compiler

COMPUTER 1996年第12期29卷 84-&页

作者： Hall, MW Anderson, JM Amarasinghe, SP Murphy, BR Liao, SW Bugnion, E Lam, MS STANFORD UNIV DEPT COMP SCISTANFORDCA 94305 STANFORD UNIV DEPT ELECT ENGNSTANFORDCA 94305

Multiple processors can work together to speed up single applications, but sequential programs must be rewritten to take advantage of the extra processors. One way to do this is through automatic parallelization with a compiler. Multiprocessors pose especially challenging problems for parallelizing compilers. Sufficient work must be performed in parallel to overcome processor synchronization and communication overhead. Moreover, multiprocessor memory hierarchies are complex, containing both shared memory and multiple levels of cache memory. Thus, two techniques are essential in obtaining good multiprocessor performance for array-based numerical programs: locating coarse-grain parallelism and managing multiprocessor memory use. The authors describe new technology in the Stanford SUIF compiler that enables it to successfully carry out these techniques. First, a suite of robust analysis techniques operate across procedure boundaries to locate coarse-grain parallelism so that large computations can execute independently in parallel. Then, to help eliminate cache misses, affine partitioning is used to improve processor reuse of data, and data permutation and data strip-mining make contiguous the data accessed by each processor in the shared address space. When employed in the automatic parallelizing compiler, these techniques significantly affect the performance of half the NAS and SPECfp95 benchmark suites.

关键词： Mathematics Computing parallelising compilers Multiprocessing Systems Performance Evaluation Optimising compilers Benchmark Programs Multiprocessor Performance SUIF Compiler Automatic Parallelization Techniques Stanford University Intermediate Format Compiler Array Based Numerical Programs Parallelizing compilers Memory Optimization Techniques Robust Analysis Techniques Speedups NAS SPE Cfp 95 Parallel Processing Phased Arrays Program Processors Information Analysis Concurrent Computing Privatization Throughput Multiprocessing Systems Cache Memory Programming Profession

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PUMA-V: Optimizing Parallel Code Performance Through Interactive Visualization

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IEEE COMPUTER GRAPHICS AND APPLICATIONS 2019年第1期39卷 84-99页

作者： Papenhausen, Eric Langston, M. Harper Meister, Benoit Lethin, Richard A. Mueller, Klaus SUNY Stony Brook Comp Sci Stony Brook NY 11794 USA Reservoir Labs Inc New York NY USA

Performance optimization for parallel loop-oriented programs compromises between parallelism and locality. We present a visualization interface that allows programmers to assist the compiler in generating optimal code. It greatly improves the user's understanding of the transformations that took place and aids in making additional transformations in a visually intuitive way.

关键词： Data Visualisation Optimisation Parallel Programming parallelising compilers Optimal Code PUMA V Optimizing Parallel Code Performance Interactive Visualization Performance Optimization Parallel Loop Oriented Programs Compromises Parallelism Locality Visualization Interface Compiler Optimization Visualization Parallel Processing Performance Evaluation Public Transportation Program Processors Image Color Analysis Open Loop Systems

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Speculative parallelization

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COMPUTER 2006年第12期39卷 126-128页

作者： Gonzalez-Escribano, Arturo Llanos, Diego R. Univ Valladolid Dept Informat E-47002 Valladolid Spain

The most promising technique for automatically parallelizing loops when the system cannot determine dependences at compile time is speculative parallelization. Also called thread-level speculation, this technique assumes optimistically that the system can execute all iterations of a given loop in parallel. A hardware or software monitor divides the iterations into blocks and assigns them to different threads, one per processor, with no prior dependence analysis. If the system discovers a dependence violation at runtime, it stops the incorrectly computed work and restarts it with correct values. Of course, the more parallel the loop, the more benefits this technique delivers. To better understand how speculative parallelization works, it is necessary to distinguish between private and shared variables. Informally speaking, private variables are those that the program always modifies in each iteration before using them. On the other hand, values stored in shared variables are used in different iterations.

关键词： System Monitoring Multi Threading parallelising compilers Program Control Structures Runtime Dependence Violation Discovery Speculative Parallelization Automatic Loop Parallelization Program Compiler Thread Level Speculation Hardware Monitor Software Monitor Program Dependence Analysis Hardware Monitoring Runtime Performance Loss Concurrent Computing Speculative Parallelization How Things Work

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Automatic Cluster Parallelization and Minimizing Communication via Selective Data Replication

Automatic Cluster Parallelization and Minimizing Communicati...

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IEEE High Performance Extreme Computing Conference (HPEC)

作者： Tavarageri, Sanket Meister, Benoit Baskaran, Muthu Pradelle, Benoit Henretty, Tom Konstantinidis, Athanasios Johnson, Ann Lethin, Richard Reservoir Labs 632 Broadway New York NY 10012 USA

ISBN: (纸本)9781467392860

The technology scaling has initiated two distinct trends that are likely to continue into future: first, the increased parallelism in hardware and second, the increasing performance and energy cost of communication relative to computation. Both of the above trends call for development of compiler and runtime systems to automatically parallelize programs and reduce communication in parallel computations to achieve the desired high performance in an energy-efficient fashion. In this paper, we propose the design of an integrated compiler and runtime system that auto-parallelizes loop-nests to clusters and, a novel communication avoidance method that reduces data movement between processors. Communication minimization is achieved via data replication: data is replicated so that a larger share of the whole data set may be mapped to a processor and hence, non-local memory accesses reduced. Experiments on a number of benchmarks show the effectiveness of the approach.

关键词： data handling parallel programming parallelising compilers power aware computing program control structures storage management automatic cluster parallelization automatic program parallelization communication avoidance method communication minimization compiler energy efficiency hardware parallelism loop-nest autoparallelization nonlocal memory access parallel computation processor data movement runtime system selective data replication technology scaling Arrays Benchmark testing Complexity theory Memory management Minimization Program processors Runtime

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A Parallelizing Matlab Compiler Framework and Run time for Heterogeneous Systems 17

A Parallelizing Matlab Compiler Framework and Run time for H...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Skalicky, Sam Lopez, Sonia Lukowiak, Marcin Schmidt, Andrew G. Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA Univ Southern Calif Inst Informat Sci Los Angeles CA 90089 USA

ISBN: (纸本)9781479989379

Compute-intensive applications incorporate ever increasing data processing requirements on hardware systems. Many of these applications have only recently become feasible thanks to the increasing computing power of modern processors. The Matlab language is uniquely situated to support the description of these compute-intensive scientific applications, and consequently has been continuously improved to provide increasing computational support in the form of multithreading for CPUs and utilizing accelerators such as GPUs and FPGAs. Moreover, to take advantage of the computational support in these heterogeneous systems from the problem domain to the computer architecture necessitates a wide breadth of knowledge and understanding. In this work, we present a framework for the development of compute-intensive scientific applications in Matlab using heterogeneous processor systems. We investigate systems containing CPUs, GPUs, and FPGAs. We leverage the capabilities of Matlab and supplement them by automating the mapping, scheduling, and parallel code generation. Our experimental results on a set of benchmarks achieved from 20x to 60x speedups compared to the standard Matlab CPU environment with minimal effort required on the part of the user.

关键词： graphics processing units mathematics computing multi-threading parallel architectures parallelising compilers FPGA GPU Matlab compiler framework Matlab language compute-intensive scientific application computer architecture heterogeneous processor system heterogeneous system multithreading parallel code generation standard Matlab CPU environment Data transfer Field programmable gate arrays Kernel MATLAB Message systems Processor scheduling Scheduling Heterogeneous computing Matlab compiler MATLAB Multithreading Field programmable gate arrays HETEROGENEOUS SYSTEM Computer Architecture Computer based information systems mathematics computing compilers scheduling of multiprocessor Code generation data transmission Parallel architectures Graphics Processing Unit central processing units

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Coarse-grain Optimization and Code Generation for Embedded Multicore Systems

Coarse-grain Optimization and Code Generation for Embedded M...

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16th Euromicro Conference on Digital System Design (DSD)

作者： Goulas, George Valouxis, Christos Alefragis, Panayiotis Voros, Nikolaos S. Gogos, Christos Oey, Oliver Stripf, Timo Bruckschloegl, Thomas Becker, Juergen El Moussawi, Ali Naullet, Maxime Yuki, Tomofumi Technol Educ Inst Mesolonghi Mesolonghi Greece Technol Educ Inst Epirus Epirus Greece Karlsruhe Inst Technol Karlsruhe Germany Univ Rennes 1 INRIA Res Inst Rennes France

ISBN: (纸本)9780769550749

As processors and systems-on-chip increasingly become multicore, parallel programming remains a difficult, time-consuming and complicated task. End users who are not parallel programming experts have a need to exploit such processors and architectures, using state of the art fourth generation of high programming languages, like Scilab or MATLAB. The ALMA toolset addresses this problem by receiving Scilab code as input and produces parallel code for embedded multiprocessor systems on chip, using platform quasi-agnostic optimisations. In this paper, coarse grain parallelism extraction and optimization issues as well as parallel code generation for the ALMA toolset are discussed.

关键词： embedded systems multiprocessing systems optimisation parallel languages parallel programming parallelising compilers system-on-chip

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Oil and Water Can Mix: An Integration of Polyhedral and AST-based Transformations 14

Oil and Water Can Mix: An Integration of Polyhedral and AST-...

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International Conference on High Performance Computing, Networking, Storage and Analysis

作者： Shirako, Jun Pouchet, Louis-Noel Sarkar, Vivek Rice Univ Houston TX 77251 USA Univ Calif Los Angeles Los Angeles CA 90024 USA

ISBN: (纸本)9781479955008

Optimizing compilers targeting modern multi-core machines require complex program restructuring to expose the best combinations of coarse-and fine-grain parallelism and data locality. The polyhedral compilation model has provided significant advancements in the seamless handling of compositions of loop transformations, thereby exposing multiple levels of parallelism and improving data reuse. However, it usually implements abstract optimization objectives, for example "maximize data reuse", which often does not deliver best performance, e.g., the complex loop structures generated can be detrimental to short-vector SIMD performance. In addition, several key transformations such as pipeline-parallelism and unroll-and-jam are difficult to express in the polyhedral framework. In this paper, we propose a novel optimization flow that combines polyhedral and syntactic/AST-based transformations. It generates high-performance code that contains regular loops which can be effectively vectorized, while still implementing sufficient parallelism and data reuse. It combines several transformation stages using both polyhedral and AST-based transformations, delivering performance improvements of up to 3x over the PoCC polyhedral compiler on Intel Nehalem and IBM Power7 multi-core processors.

关键词： optimising compilers parallelising compilers AST-based transformations IBM Power7 multicore processor Intel Nehalem multicore processor PoCC polyhedral compiler abstract optimization coarse-grain parallelism complex loop structures data locality data reuse maximization data reusing fine-grain parallelism high-performance code generation loop transformations multicore machines optimization flow optimizing compilers pipeline-parallelism polyhedral compilation model polyhedral framework polyhedral-based transformations program restructuring seamless composition handling short-vector SIMD performance syntactic-based transformation transformation stages unroll-and-jam Arrays Data models Nickel Optimization Parallel processing Schedules Silicon Optimising compilers locality data data models PARALLEL PROCESSING (COMPUTERS) microparticles Nickel parallelism Silicon Synclitism

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TILT: A MULTITHREADED VLIW SOFT PROCESSOR FAMILY

TILT: A MULTITHREADED VLIW SOFT PROCESSOR FAMILY

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23rd International Conference on Field Programmable Logic and Applications (FPL)

作者： Ovtcharov, Kalin Tili, Ilian Steffan, J. Gregory Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781479900046

We propose TILT, an FPGA-based compute engine designed to highly-utilize multiple, varied, and deeply-pipelined functional units by leveraging thread-level parallelism and static compiler analysis and scheduling. For this work we focus on deeply-pipelined floating-point functional units of widely-varying latency, executing Hodgkin-Huxley neuron simulation as an example application, compiled with our LLVM-based scheduler. Targeting a Stratix IV FPGA, we explore architectural trade-offs by measuring area and throughput for designs with varying numbers of functional units, thread contexts, and memory banks.

关键词： field programmable gate arrays multi-threading multiprocessing systems parallelising compilers processor scheduling program diagnostics

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Enabling FPGA support in MATLAB based Heterogeneous Systems

Enabling FPGA support in MATLAB based Heterogeneous Systems

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Skalicky, Sam Kwolek, Tyler Lopez, Sonia Lukowiak, Marcin Rochester Inst Technol Rochester NY 14623 USA

ISBN: (纸本)9781479959440

FPGAs have been shown to provide orders of magnitude improvement over CPUs and GPUs in terms of absolute performance and energy efficiency for various kernels such as Cholesky decomposition, matrix inversion, and FFT among others. Despite this, the overall performance of many applications suffer when implemented entirely in FPGAs. Combining FPGAs with CPUs and GPUs provides the range of capabilities needed to support diverse computational requirements of applications. Integrating FPGAs into these systems challenges application developers with constructing hardware kernel implementations and interfacing from the low level hardware logic in the FPGA to the high speed networks that connect processors in the system. In this work we extend the compute capabilities of MATLAB by incorporating support for FPGAs and automating the parallel code generation. We characterize the system and evaluate the performance gains that can be achieved by adding the FPGA for two compute intensive applications. We present performance results for medical imaging and fluid dynamics applications implemented in a CPU+GPU+FPGA system and achieved up to 40x improvement compared to the standard MATLAB CPU+GPU environment.

关键词： computational fluid dynamics fast Fourier transforms field programmable gate arrays graphics processing units mathematics computing matrix inversion medical image processing multiprocessing systems parallel processing parallelising compilers CPU Cholesky decomposition FFT FPGA support GPU MATLAB based heterogeneous systems absolute performance application development computational requirements compute intensive application energy efficiency fluid dynamics application hardware kernel implementation high speed network low level hardware logic medical imaging parallel code generation performance gains processor connection Field programmable gate arrays Graphics processing units Hardware Instruction sets Kernel MATLAB

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Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays

Symbolic Parallelization of Loop Programs for Massively Para...

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IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Teich, Juergen Tanase, Alexandru Hannig, Frank Univ Erlangen Nurnberg Dept Comp Sci Nurnberg Germany

ISBN: (纸本)9781479904945;9781479904938

In this paper, we present a first solution to the unsolved problem of joint tiling and scheduling a given loop nest with uniform data dependencies symbolically. This problem arises for loop programs for which the iterations shall be optimally scheduled on a processor array of unknown size at compile-time. Still, we show that it is possible to derive parameterized latency-optimal schedules statically by proposing two new program transformations: In the first step, the iteration space is tiled symbolically into orthotopes of parametrized extensions. The resulting tiled program is subsequently scheduled symbolically. Here, we show that the maximal number of potential optimal schedules is upper bounded by 2(n)n! where n is the dimension of the loop nest. However, the real number of optimal schedule candidates being much less than this. At run-time, once the size of the processor array becomes known, simple comparisons of latency-determining expressions finally steer which of these schedules will be dynamically activated and the corresponding program configuration executed on the resulting processor array so to avoid any further run-time optimization or expensive re-compilations.

关键词： parallel processing parallelising compilers processor scheduling program control structures

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