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An intelligent parallel loop scheduling for parallelizing compilers

JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 2000年第2期16卷 169-200页

作者： Fann, YW Yang, CT Tseng, SS Tsai, CJ Natl Chiao Tung Univ Dept Comp & Informat Sci Hsinchu 300 Taiwan Natl Space Program Off ROCSAT Ground Syst Sect Hsinchu 300 Taiwan

In this paper we propose a knowledge-based approach to solving loop-scheduling problems. A rule-based system, called IPLS, is developed by combining a repertory grid and an attribute ordering table to construct a knowledge base. IPLS chooses an appropriate scheduling algorithm by inferring some features of loops and assigning parallel loops to multiprocessors to achieve significant speedup. Because more attributes are proposed, the accuracy of selection of an appropriate scheduling method is improved. In addition, the refined IPLS system can automatically adjust the attributes in the knowledge base according to profile information;therefore, IPLS has the capability of feedback learning. The experimental results show that our approach can achieve greater speedup on multiprocessor systems than can others.

关键词： parallelizing compiler parallel loop scheduling knowledge-based system multiprocessor systems speedup

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POEMS: End-to-end performance design of large parallel adaptive computational systems

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 2000年第11期26卷 1027-1048页

作者： Adve, VS Bagrodia, R Browne, JC Deelman, E Dube, A Houstis, EN Rice, JR Sakellariou, R Sundaram-Stukel, DJ Teller, PJ Vernon, MK Univ Illinois Dept Comp Sci Urbana IL 61801 USA Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA Univ Texas Dept Comp Sci Austin TX 78712 USA Purdue Univ Dept Comp Sci W Lafayette IN 47907 USA Univ Manchester Dept Comp Sci Manchester M13 9PL Lancs England Univ Wisconsin Dept Comp Sci Madison WI 53706 USA Univ Texas Dept Comp Sci El Paso TX 79968 USA

The POEMS project is creating an environment for end-to-end performance modeling of complex parallel and distributed systems, spanning the domains of application software, runtime and operating system software, and hardware architecture. Toward this end. the POEMS framework supports composition of component models from these different domains into an end-to-end system model. This composition can be specified using a generalized graph model of a parallel system, together with interface specifications that carry information about component behaviors and evaluation methods. The POEMS Specification Language compiler, under development, will generate an end-to-end system model automatically from such a specification. The components of the target system may be modeled using different modeling paradigms (analysis, simulation, or direct measurement) and may be modeled at various levels of detail. As a result, evaluation of a POEMS end-to-end system model may require a variety of evaluation tools including specialized equation solvers, queuing network solvers, and discrete-event simulators. A single application representation based on static and dynamic task graphs serves as a common workload representation for all these modeling approaches. Sophisticated parallelizing compiler techniques allow this representation to be generated automatically for a given parallel program. POEMS includes a library of predefined analytical and simulation component models of the different domains and a knowledge base that describes performance properties of widely used algorithms. This paper provides an overview of the POEMS methodology and illustrates several of its key components. The methodology and modeling capabilities are demonstrated by predicting the performance of alternative configurations of Sweep3D, a complex benchmark for evaluating wavefront application technologies and high-performance, parallel architectures.

关键词： performance modeling parallel system message passing analytical modeling parallel simulation processor simulation task graph parallelizing compiler compositional modeling recommender system

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Efficient interprocedural array data-flow analysis for automatic program parallelization

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 2000年第3期26卷 244-261页

作者： Gu, JJ Li, ZY Sun Microsyst Inc Palo Alto CA 94303 USA Purdue Univ Dept Comp Sci W Lafayette IN 47907 USA

Since sequential languages such as Fortran and C are more machine-independent than current parallel languages, it is highly desirable to develop powerful parallelization-tools which can generate parallel codes, automatically or semiautomatically, targeting different parallel architectures. Array data-flow analysis is known to be crucial to the success of automatic parallelization. Such an analysis should be performed interprocedurally and symbolically and it often needs to handle the predicates represented by IF conditions. Unfortunately, such a powerful program analysis can be extremely time-consuming if not carefully designed. How to enhance the efficiency of this analysis to a practical level remains an issue largely untouched to date. This paper presents techniques for efficient interprocedural array data-flow analysis and documents experimental results of its implementation in a research parallelizing compiler. Our techniques are based on guarded array regions and the resulting tool runs faster, by one or two orders of magnitude, than other similarly powerful tools.

关键词： parallelizing compiler array data-flow analysis interprocedural analysis symbolic analysis

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A practical run-time technique for exploiting loop-level parallelism

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JOURNAL OF SYSTEMS AND SOFTWARE 2000年第3期54卷 259-271页

作者： Huang, TC Hsu, PH Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung 804 Taiwan

In order to exploit potential parallelism of loops, in which the array access patterns cannot be analyzed at compile-time, parallelizing compilers must rely on the run-time dependence analysis techniques. The LRPD test is noted in this field for its applicability. It assumes full parallelism and executes speculatively, then examines the correctness of parallel execution after loop termination. We extended the concept and developed a practical run-time technique, called the speculative parallelization with new technology (SPNT) test, to further exploit loop-level parallelism. Two main characteristics make the SPNT test distinguished. The first is improving the success rate of speculative parallelization by eliminating all cross-iteration data dependences except the cross-processory flow dependences. The second is reducing the failure penalty by aborting the speculative parallel execution immediately once a cross-processor flow dependence is detected during the execution. Our experimental results on shared-memory parallel machines lip SPP2000 and ALR QUAD6 prove the high effectiveness of the SPNT test. (C) 2000 Elsevier Science Inc. All rights reserved.

关键词： parallelizing compiler data dependence analysis run-time technique speculative parallelization inspector/executor

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NUAPC: A parallelizing compiler for C++

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Journal of Computer Science & Technology 1997年第5期12卷 458-459页

作者：朱根江谢立孙钟秀 DepartmentofComputerScience NationalKeyLabforNovelSoftwareTechnologyNanjingUniversityNanjing210093

This paper presents a model for automatically parallelizing compiler based on C++ which consists of compile-time and run-time parallelizing *** paper also describes a method for finding both intra-object and inter-obj... 详细信息

关键词： parallelizing compiler data dependence object-oriented programming distributed discrete-event simulation

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An object-oriented framework for loop parallelization

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JOURNAL OF SUPERCOMPUTING 1999年第1期13卷 57-69页

作者： Omori, Y Fukuda, A Nara Inst Sci & Technol Grad Sch Informat Sci Nara 6300101 Japan Wakayama Univ Fac Syst Engn Wakayama 6408441 Japan

Generation of efficient parallel code is a major goal of a well-designed and developed parallelizing compiler. Another important goal is portability of both compiler system and the resulting output source codes. The various choices of current and future parallel computer architectures as well as the cost of developing a parallelizing compiler make portability a very important design goal. Since the design of parallelizing compilers is considerably move complex than designing conventional compilers, it is very important to achieve both efficiency and portability. To meet this dual goal, we have investigated the application of object oriented design to parallelizing compilers. Our parallelizing compiler design is based on abstractions of intermediate representations of loops and their class definitions. In this paper, we address the problem of loop parallelization and propose a framework where the loop parallelization process is divided into three phases and the optimization of loops is performed via a cyclic application of these three phases. The class of each phase is hierarchically derived from intermediate representations of loops. This facilitates the portability of the resulting parallelizing compilers. Furthermore, one of the phases uses a reservation table of hardware resources in order to obtain optimized parallel programs for given hardware resources. The validation of the proposed framework is given through the application of the object oriented design on an example program which is then parallelized efficiently.

关键词： object-oriented design parallelizing compiler loop parallelization OMT portability

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Communication set generations with CSD calculus and expression-rewriting framework

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PARALLEL COMPUTING 1999年第9期25卷 1105-1130页

作者： Hwang, GH Lee, JK Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30043 Taiwan

In this paper, we present a new framework based on expression-rewritings and a calculus form called common-stride descriptor (CSD) calculus to generate the local enumeration set and communication set for High Performance Fortran (HPF) programs with 'Block-Cyclic' distributions. Our framework is a practical software framework, and can handle the general cases so that the communication set of HPF programs of block-cyclic distributions with two-level alignments (or multiple-level alignments), multi-dimensional arrays, array intrinsic functions (such as Transpose operation), and affine indices and axis exchanges in the array subscript, can be calculated in a systematic way with a sound software foundation. Previously, existing works do not report a software framework to solve a problem with such general cases. In addition, our expression-rewriting framework is based on a new representative form, CSD, to describe the regularity of the access patterns of HPF programs with block-cyclic distribution. We also demonstrate a calculus of CSD that CSD is closed under intersection and normalization, which helps the process of calculating local enumeration and communication sets of HPF programs with block-cyclic distributions. We also utilize the characteristics of CSD calculus to provide a global-to-local mapping function for multiple level alignments and block-cyclic distributions. Experimental results show that our software scheme not only can be easily implemented in the practice, but also is with good efficiency (C) 1999 Elsevier Science B.V. All rights reserved.

关键词： HPF compiler distributed memory machines compiler optimization parallelizing compiler block-cyclic distributions

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Efficient implementation of multi-dimensional array redistribution

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1998年第11期E81D卷 1195-1204页

作者： Guo, MY Yamashita, N Nakata, I Univ Tsukuba Doctoral Program Engn Tsukuba Ibaraki 3050006 Japan

Array redistribution is required very often in programs on distributed memory parallel computers. It is essential to use efficient algorithms for redistribution, otherwise the performance of programs may degrade considerably. In this paper, we focus on automatic generation of communication routines for multi-dimensional redistribution. The principal advantage of this work is to gain the ability to handle redistribution between arbitrary source and destination processor sets and between arbitrary source and destination distribution schemes. We have implemented these algorithms using Parallelware communication library. Some experimental results show the efficiency and flexibility of our techniques compared to the other redistribution works.

关键词： parallelizing compiler array redistribution distributed memory parallel computers interprocessor communication data parallel language

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Eliminating barrier synchronization for compiler-parallelized codes on software DSMs

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 1998年第5期26卷 591-612页

作者： Han, HS Tseng, CW Keleher, P Univ Maryland Dept Comp Sci College Pk MD 20742 USA

Software distributed-shared-memory (DSM) systems provide an appealing target for parallelizing compilers due to their flexibility. Previous studies demonstrate such systems can provide performance comparable to message-passing compilers for dense-matrix kernels. However, synchronization and load imbalance are significant sources of overhead. In this paper, we investigate the impact of compilation techniques for eliminating barrier synchronization overhead in software DSMs. Our compile-time barrier elimination algorithm extends previous techniques in three ways: (1) we perform inexpensive communication analysis through local subscript analysis when using chunk iteration partitioning for parallel loops;(2) we exploit delayed updates in lazy-release-consistency DSMs to eliminate barriers guarding only anti-dependences;(3) when possible we replace barriers with customized nearest-neighbor synchronization. Experiments on an IBM SP-2 indicate these techniques can improve parallel performance by 20% on average and by up to 60% for some applications.

关键词： eliminating barrier parallelizing compiler software DSM

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Improving performance of multi-dimensional array redistribution on distributed memory machines 3

Improving performance of multi-dimensional array redistribut...

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3rd International Workshop on High-Level Parallel Programming Models and Supportive Environments at the IPPS/SPDP 1998

作者： Guo, M Yamashita, Y Nakata, I Univ Tsukuba Tsukuba Ibaraki 305 Japan

ISBN: (纸本)0818684127

Array redistribution is required very often in programs on distributed memory parallel computers. It is essential to use efficient algorithms for redistribution, otherwise the performance of the programs may degrade considerably. In this paper, we focus on automatic generation of communication routines for multidimensional redistribution. The principal advantage of this work is to gain the ability to handle redistribution between arbitrary source and destination processor sets and between arbitrary source and destination distribution schemes. We have implemented these algorithms using Parallelware communication library. Some optimization techniques for our algorithms are also proposed in this paper. Experimental results show the efficiency and flexibility of our techniques compared to the other redistribution works.

关键词： parallelizing compiler HPF array redistribution automatic data distribution automatic parallelization and optimization

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