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7th International Conference on Quality Software

作者： Tefft, Robert A. Lee, Roger Y. Cent Michigan Univ Dept Comp Sci Mt Pleasant MI 48859 USA Cent Michigan Univ SEITI Mt Pleasant MI 48859 USA

ISBN: (纸本)9780769530352

SHAM (Single Instruction Multiple Data) is a processor-architecture classification from Flynn's taxonomy. The concept is that a single instruction set operates on multiple units of data simultaneously. Computers use this processor architecture are known as array processors or vector processors. Most computers in use today are SISD (single instruction single data) though allowing a single instruction to operate on multiple data can also be applied to a virtual machine that is capable of parallel execution through the use of multi-threading/multi-core processors, or distributed parallel execution on a multi-computer grid. This paper proposes a language structure that applies the SIMD concept to the Java virtual machine. The motive is to reduce the complexity of the code and ease implementation of parallelization by running a single set of instructions concurrently on an entire collection of objects.

关键词： concurrency control parallel languages parallel processing parallel programming parallelizing compilers vector processing

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Automatic Parallelization of Python Programs for Distributed Heterogeneous Computing 28th

Automatic Parallelization of Python Programs for Distributed...

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28th International Conference on Parallel and Distributed Computing (Euro-Par)

作者： Shirako, Jun Hayashi, Akihiro Paul, Sri Raj Tumanov, Alexey Sarkar, Vivek Georgia Inst Technol Atlanta GA 30332 USA Intel Corp Austin TX 78746 USA

ISBN: (纸本)9783031125973;9783031125966

This paper introduces a new approach to automatic ahead-of-time (AOT) parallelization and optimization of sequential Python programs for execution on distributed heterogeneous platforms. Our approach enables AOT source-to-source transformation of Python programs, driven by the inclusion of type hints for function parameters and return values. These hints can be supplied by the programmer or obtained by dynamic profiler tools;multi-version code generation guarantees the correctness of our AOT transformation in all cases. Our compilation framework performs automatic parallelization and sophisticated high-level code optimizations for the target distributed heterogeneous hardware platform. It introduces novel extensions to the polyhedral compilation framework that unify user-written loops and implicit loops present in matrix/tensor operators, as well as automated selection of CPU vs. GPU code variants. Finally, output parallelized code generated by our approach is deployed using the Ray runtime for scheduling distributed tasks across multiple heterogeneous nodes in a cluster, thereby enabling both intra-node and inter-node parallelism. Our empirical evaluation shows significant performance improvements relative to sequential Python in both single-node and multi-node experiments, with a performance improvement of over 20,000x when using 24 nodes and 144 GPUs in the OLCF Summit supercomputer for the Space-Time Adaptive Processing (STAP) radar application.

关键词： parallelizing compilers Python language Parallel computing Heterogeneous computing Distributed computing

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Parallelization with Automatic parallelizing Compiler Generating Consumer Electronics Multicore API

Parallelization with Automatic Parallelizing Compiler Genera...

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IEEE International Symposium on Parallel and Distributed Processing with Applications

作者： Miyamoto, Takamichi Asaka, Saori Mikami, Hiroki Mase, Masayoshi Wada, Yasutaka Nakano, Hirofumi Kimura, Keiji Kasahara, Hironori Waseda Univ Dept Comp Sci & Engn Shinjuku Ku Tokyo 1698555 Japan

ISBN: (纸本)9780769534718

Multicore processors have been adopted for consumer electronics like portable electronics, mobile phones, car navigation systems, digital TVs and games to obtain high performance with low power consumption. The OSCAR automatic parallelizing compiler has been developed to utilize these multicores easily. Also, a new Consumer Electronics Multicore Application Program Interface (API) to use the OSCAR compiler with native sequential compilers for various kinds of multicores from different vendors has been developed in NEDO (New Energy and Industrial Technology Development Organization) "Multicore Technology for Realtime Consumer Electronics" project with Japanese 6 IT companies. This paper evaluates the parallel processing performance of multimedia applications using this API by the OSCAR compiler on the FR1000 4 VLIW cores multicore processor developed by Fujitsu Ltd, and the RP1 4 SH-4A cores multicore processor jointly-developed by Renesas Technology Corp., Hitachi Ltd. and Waseda University. As the results, the parallel codes generated by the OSCAR compiler using the API give us 3.27 times speedup on average using 4 cores against 1 core on the FR1000 multicore, and 3.31 times speedup on average using 4 cores against 1 core on the RP1 multicore.

关键词： application program interface automatic parallelizing compiler multicore multimedia application Multi-core processors MULTIMEDIA APPLICATION consumer electronics parallelizing compilers parallelization Speeding compilers

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Data dependence analysis techniques for increased accuracy and extracted parallelism

Data dependence analysis techniques for increased accuracy a...

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17th International Conference on Supercomputing

作者： Kyriakopoulos, K Psarris, K Univ Texas Dept Comp Sci San Antonio TX 78249 USA

parallelizing compilers rely on data dependence information in order to produce valid parallel code. Traditional data dependence analysis techniques, such as the Banerjee test and the I-Test, can efficiently compute data dependence information for simple instances of the data dependence problem. However, in more complex cases involving triangular or trapezoidal loop regions, symbolic variables, and multidimensional arrays with coupled subscripts these tests, including the triangular Banerjee test, ignore or simplify many of the constraints and thus introduce approximations, especially when testing for data dependence under direction vector constraints. The Omega test can accurately handle such complex cases, but at a higher computation cost. In this paper we extend the ideas behind the I-Test and present new techniques to handle complex instances of the dependence problem, which are frequently found in actual source code. In particular, we provide polynomial-time techniques that can prove or disprove data dependences, subject to any direction vector, in loops with triangular or trapezoidal bounds, symbolic variables, and multidimensional arrays with coupled subscripts. We also investigate the impact of the proposed data dependence analysis techniques in practice. We perform an extensive experimental evaluation of the data dependence analysis tests, including the I-Test, the Omega test and the proposed new techniques. We compare these tests in terms of data dependence accuracy, compilation efficiency and effectiveness in program parallelization. We run several experiments using the Perfect Club benchmarks and the scientific library Lapack. We analyze the trade-off between accuracy and efficiency and the reasons for any approximation of each data dependence test. We determine the impact of the dependence analysis phase on the total compilation time and we measure the number of loops parallelized by each test. We conclude that we can employ polynomial-time techniques t

关键词： parallelizing compilers data dependence program analysis automatic parallelization compiler optimization

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Efficient communication optimization for irregular array references

Efficient communication optimization for irregular array ref...

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2nd International Conference on Computer and Information Technology (CIT'2001)

作者： Guo, M.-Y. Lio, Z. School of Computer Science and Eng. University of Aizu Aizu-Wakamatsu Fukushima 965-8580 Japan

Communication set generation significantly influences the performance of parallel programs. However, seldom work gives attention to the communication generation problem for irregular applications. In this paper, we propose some communication optimization techniques for the situation of irregular array references in nest loops. In our methods, the local array distribution schemes are determined such that the total amount of communication messages is minimum. Then, we explain how to support communication set generation at compile-time by introducing some symbolic analysis techniques. In our symbolic analysis system, a set of symbolic solutions of a symbolic expression system is solved by limiting some restrictions. Finally, we show experimental results on a parallel computer CM-5 that validate our approach.

关键词： Communication optimization Distributed memory multicomputers Irregular array references parallelizing compilers Symbolic analysis

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Extraction of Recursion Level Parallelism for Embedded Multicore Systems 17

Extraction of Recursion Level Parallelism for Embedded Multi...

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17th Annual International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS)

作者： Aguilar, Miguel Angel Leupers, Rainer Ascheid, Gerd Eusse, Juan Fernando Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silex GmbH Herne Germany

ISBN: (纸本)9781538634370

Recursive programs that typically implement divide-and-conquer algorithms are well-suited for multicore systems, as they offer a high degree of parallelization potential. So far, existing parallelizing compilers have mainly focused on extracting other parallel patterns, such as data or pipeline level parallelism. In this paper, we propose a toolflow for the extraction of recursion level parallelism for embedded multicore systems. To achieve this, the toolflow verifies not only the mutual independence of recursive call-sites, but also selects an appropriate task granularity to ensure a good trade-off between load balancing and parallelization overhead. Profitable parallelization opportunities are implemented by using compiler directives from the OpenMP tasking model. Results show the effectiveness of our toolflow, as it is able to speedup sequential recursive programs between 2.5x and 3.8x on a quad-core platform.

关键词： Task analysis Multicore processing Parallel processing Analytical models Performance analysis Static analysis Load management task analysis load management PARALLEL PROCESSING (COMPUTERS) ANALYSIS MODELS Multi-core processors parallelism Synclitism Recursion Recursive Procedure parallelizing compilers parallelization

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What computer architecture can learn from computational intelligence - and vice versa

What computer architecture can learn from computational inte...

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23rd Euromicro Conference on New Frontiers of Information Technology

作者： Moore, R Klauer, B Waldschmidt, K J. W. Goethe-University Technische Informatik 60054 Frankfurt P.O. Box 111932 Germany

ISBN: (纸本)0818681306

This paper considers whether the seemingly disparate fields of Computational Intelligence (CI) and computer architecture can profit from each others' principles, results and experience. In the process, we identify important common issues, such as parallelism, distribution of data and control, granularity and regularity. We present two novel computer architectures which have profited from principles found in CI, and identify two constraints on CI to eliminate the hidden influence of the von Neumann model of computation.

关键词： Memory systems and management Multithreaded Architecture Neuro-Computing Parallel and Distributed Systems parallelizing compilers

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PROPERTIES OF SIMULATED ANNEALING AND GENETIC ALGORITHMS FOR MAPPING DATA TO MULTICOMPUTERS

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Parallel Algorithms and Applications 1997年第4期12卷 279-296页

作者： Nashat Mansour[a] Jalal Kawash[a] Hassan Diab[b] [a] Lebanese American University Computer Science Program Beirut Lebanon [b] American University of Beirut Electrical Engineering Dept. Beirut Lebanon

We experimentally analyze some properties of simulated annealing algorithms (SA) and genetic algorithms (GA) for mapping data to multicomputers. These properties include sensitiviiy to user parameters, fault tolerance capability, and applicability to different multicomputer topologies. Some user parameters are included in the objective function and are architecture- or problem-dependent parameters. The others are used in the GA and SA algorithms. The fault tolerance capability is demonstrated by mapping data to a multicomputer with some faulty processors. We assume a hypercube multicomputer architecture in most experiments. However, mapping to mesh, array, ring, tree, and star graph topologies is also demonstrated. The experimental results show that the GA and SA are insensitive to user parameters in wide ranges, completely fault tolerant, and unbiased towards particular multicomputer topologies. These properties of flexibility and general applicability, which are lacking in other heuristic algorithms, make the GA and SA attractive for automatic parallelization systems.

关键词： automatic parallelization data mapping load partitioning and balancing scheduling parallelizing compilers

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RUNTIME AND LANGUAGE SUPPORT FOR COMPILING ADAPTIVE IRREGULAR PROGRAMS ON DISTRIBUTED-MEMORY MACHINES

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SOFTWARE-PRACTICE & EXPERIENCE 1995年第6期25卷 597-621页

作者： HWANG, YS MOON, B SHARMA, SD PONNUSAMY, R DAS, R SALTZ, JH SYRACUSE UNIV NW PARALLET ARCHITECTURES CTR SYRACUSE NY 13244 USA UNIV MARYLAND UMIACS COLLEGE PK MD 20742 USA

In many scientific applications, arrays containing data are indirectly indexed through indirection arrays. Such scientific applications are called irregular programs and are a distinct class of applications that require special techniques for parallelization. This paper presents a library called CHAOS, which helps users implement irregular programs on distributed-memory message-passing machines, such as the paragon, Delta, CM-5 and SP-1. The CHAOS library provides efficient runtime primitives for distributing data and computation over processors;it supports efficient index translation mechanisms and provides users high-level mechanisms for optimizing communication. CHAOS subsumes the previous PARTI library and supports a larger class of applications. In particular, it provides efficient support for parallelization of adaptive irregular programs where indirection arrays are modified during the course of computation. To demonstrate the efficacy of CHAOS, two challenging real-life adaptive applications were parallelized using CHAOS primitives: a molecular dynamics code, CHARMM, and a particle-in-cell code, DSMC. Besides providing runtime support to users, CHAOS tan also be used by compilers to automatically parallelize irregular applications. This paper demonstrates how CHAOS can be effectively used in such a framework. By embedding CHAOS primitives in the Syracuse Fortran 90D/HPF compiler, kernels taken from the CHARMM and DSMC codes have been automatically parallelized.

关键词： DISTRIBUTED-MEMORY MULTIPROCESSORS RUNTIME COMPILATION ADAPTIVE IRREGULAR PROGRAMS parallelizing compilers

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ACCESS NORMALIZATION - LOOP RESTRUCTURING FOR NUMA COMPUTERS

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ACM TRANSACTIONS ON COMPUTER SYSTEMS 1993年第4期11卷 353-375页

作者： LI, W PINGALI, K Department of Computer Science Cornell University Ithaca NY 14853 United States

In scalable parallel machines, processors can make local memory accesses much faster than they can make remote memory accesses. Additionally, when a number of remote accesses must be made, it is usually more efficient to use block transfers of data rather than to use many small messages. To run well on such machines, software must exploit these features. We believe it is too onerous for a programmer to do this by hand, so we have been exploring the use of restructuring compiler technology for this purpose. In this article, we start with a language like HPF-Fortran with user-specified data distribution and develop a systematic loop transformation strategy called access normalization that restructures loop nests to exploit locality and block transfers. We demonstrate the power of our techniques using routines from the BLAS (Basic Linear Algebra Subprograms) library. An important feature of our approach is that we model loop transformations using invertible matrices and integer lattice theory.

关键词： ALGORITHMS EXPERIMENTATION LANGUAGES PERFORMANCE COMMUNICATION DATA LOCALITY LOOP TRANSFORMATION NONSINGULAR LOOP TRANSFORMATION NONUNIFORM MEMORY ACCESS MACHINES parallelizing compilers

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