We present a fault-tolerant quantum computing architecture based on a code concatenation of the parity code. In addition to the recently explored concatenation with bosonic (i.e. continuous-variable) qubits, we propos...
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ISBN:
(纸本)9798331541378
We present a fault-tolerant quantum computing architecture based on a code concatenation of the parity code. In addition to the recently explored concatenation with bosonic (i.e. continuous-variable) qubits, we propose and study a concatenation with discrete-variable stabilizer codes. The parity code can be understood as a low-density-parity-check (LDPC) code tailored specifically to obtain any desired logical connectivity from nearest neighbor physical interactions. On the bosonic side, the proposed scheme enables codes with better encoding rate compared to the repetition code with the same code distances, while requiring only weight-3 and weight-4 stabilizers and nearest neighbor 2D square-lattice connectivity. On the discrete-variable side, the proposed scheme enables Calderbank-Shor-Steane (CSS) codes with less physical qubits overhead compared to the surface code but they do not form a quantum LDPC family.
We present a single framework to describe parity codes in exclusively spatial dimensions as quantum error correction codes, as well as parity codes with a temporal dimension, as quantum circuits. This framework builds...
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ISBN:
(纸本)9798331541378
We present a single framework to describe parity codes in exclusively spatial dimensions as quantum error correction codes, as well as parity codes with a temporal dimension, as quantum circuits. This framework builds on the stabilizer formalism to introduce label tracking of parity information for illustrating and constructing quantum circuits and quantum error correction codes. Additionally, this framework proposes the necessary transformations and conditions to translate between the spatial and temporal versions of a given parity code. This technique is then applied to find the temporal variant of the spatially extended LHZ-code [I] using CNOT gates on a linear nearest -neighbor (LNN) qubit architecture. The resulting quantum circuit provides an efficient implementation of quantum algorithms on LNN architectures, that require the interactions found in all -to -all connected transverse -field Ising models. Two widely used quantum algorithms that require such interactions are the Quantum Approximate Optimization Algorithm (QAOA) 121 and the quantum Fourier transform (QFT). For the QAOA, this is the first proposal with a linear circuit depth while not requiring more than n(2) CNOT gates per iteration. Our approach for QFT, requiring only LNN connectivity, surpasses previous (NT implementations even on devices with high qubit connectivity in terms of circuit depth while not increasing the gate count in leading order.
In space applications, cosmic radiation-induced multiple cells upset (MCU) poses a major stability issue for static random-access memory (SRAM). During the past decade, radiation-induced MCUs have been responsible for...
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We propose a new structure of a self-checking combinational device where, based on the properties of parity and Berger codes, as well as a code with the detection of all double errors in information vectors, the probl...
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We propose a new structure of a self-checking combinational device where, based on the properties of parity and Berger codes, as well as a code with the detection of all double errors in information vectors, the problem of detecting all single faults of logical elements can be solved without transforming the structure of the source device. The properties of binary codes with the detection of all double errors that can be used in constructing the proposed structure are considered. We give an example of constructing a new structure.
Proposed were new structures for concurrent error detection systems of the combinatorial logic circuits based on the codes with summation of the weighted transitions and their modifications. They were compared with th...
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Proposed were new structures for concurrent error detection systems of the combinatorial logic circuits based on the codes with summation of the weighted transitions and their modifications. They were compared with the traditional systems of duplication and check by the Berger code. The structure based on the code with summation of the weighted transitions allowed one to improve the index of realization complexity as compared with the duplication system by 4 % on the average. The structure obtained by modifying the code with summation of the weighted transitions into the optimal code enables one to improve this index almost twice as much as compared with the system of checking by the Berger code. At that, this system has a better index of error detection. In certain cases, the structure of the concurrent error detection system on the basis of the optimal code is superior in complexity to the system of parity check.
Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible componen...
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Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible component to soft errors. Error detection and correction codes are common protection techniques for cache memory due to their design simplicity. In order to design effective protection techniques for caches, it is important to quantitatively estimate the susceptibility of caches without and even with protections. At the architectural level, vulnerability is the metric to quantify the susceptibility of data in caches. However, existing tools and techniques calculate the vulnerability of data in caches through coarse-grained block-level estimation. Further, they ignore common cache protection techniques such as error detection and correction codes. In this article, we demonstrate that our word-level vulnerability estimation is accurate through intensive fault injection campaigns as compared to block-level one. Further, our extensive experiments over benchmark suites reveal several counter-intuitive and interesting results. parity checking when performed over just reads provides reliable and power-efficient protection than that when performed over both reads and writes. On the other hand, checking error correcting codes only at reads alone can be vulnerable even for single-bit soft errors, while that at both reads and writes provides the perfect reliability.
This paper explores the effectiveness of error detection schemes in increasingly multiple-cell upset-dominant technologies, specifically SRAM. A review of interleaving distance, parity codes, and well-taps is conducte...
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This paper explores the effectiveness of error detection schemes in increasingly multiple-cell upset-dominant technologies, specifically SRAM. A review of interleaving distance, parity codes, and well-taps is conducted to examine each attribute. Then, the paper proposes a novel error detection scheme with the harmonious use of the multiple-cell upset inhibition effects of well-taps, the detectability of parity codes, and an interleaving distance scheme to create an effective error detection scheme that is both flexible and has a high implementation prospect. A row depth model is created to assess the effectiveness of the proposed scheme. The model shows that advanced technologies with greater multiple-cell upset sizes and ratios will experience error detection failures with schemes such as single error correction-double error detection, whereas the proposed scheme remains effective. Experimental data supports the premise that well-taps inhibit multiple-cell upset, as it is found that 1% cross well-taps. The proposed scheme is recognized to be at least three times better against error detection failures than single error correction-double error detection.
Hamming code is a parity code, the information bits and test bits must be mixed arrangement at a fixed location to check for errors s and correct the wrong. Based on the design principle of Hamming codes, this paper g...
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ISBN:
(纸本)9783642240966
Hamming code is a parity code, the information bits and test bits must be mixed arrangement at a fixed location to check for errors s and correct the wrong. Based on the design principle of Hamming codes, this paper gives a improved method, proposed to arrangements the test bits in the last digit of code word, so that extract the information hit more convenient, and hardware implementation will be easier.
Hamming code is a parity code, the information bits and test bits must be mixed arrangement at a fixed location to check for errors s and correct the wrong. Based on the design principle of Hamming codes, this paper g...
详细信息
Hamming code is a parity code, the information bits and test bits must be mixed arrangement at a fixed location to check for errors s and correct the wrong. Based on the design principle of Hamming codes, this paper gives a improved method, proposed to arrangements the test bits in the last digit of code word, so that extract the information bit more convenient, and hardware implementation will be easier.
In magnetic recording, a standard code architecture consists of an outer Reed-Solomon code in concatenation with an inner parity code. The inner parity code is used to detect and correct common error events. Generally...
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In magnetic recording, a standard code architecture consists of an outer Reed-Solomon code in concatenation with an inner parity code. The inner parity code is used to detect and correct common error events. Generally, a parity code with short block length performs better, as multiple error events within one block and, consequently, miscorrection are less likely. In this paper, we study an inner code that offers the same system performance as a parity code with very short block length, even as short as the symbol length (in bits) of the outer Reed-Solomon code, but with higher code rate. This code is a tensor-product code, with a Bose-Chauduri-Hocquenghem (BCH) code and a short parity code as constituent codes. The decoder for this code is not much more complex than the optimal decoder of the baseline parity-coded channel;in fact, the only additional steps are Viterbi detection matched to the channel and decoding of the BCH code.
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