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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Jigang Wu Guiyuan Jiang Lili Zheng Suiping Zhou School of Computer Science and Software Engineering Tianjin Polytechnic University Tianjin China The State Key Laboratory of Computer Science Chinese Academy of Sciences Beijing China School of Computer Science and Technology Tianjin University Tianjin China School of Science and Technology Middlesex University London United Kingdom

ISBN: (纸本)9781479961245

Graph partitioning has been widely applied in cloud computing, data centres, virtual machine scheduling, hardware/software co-design, and VLSI circuit design, etc. The general graph partitioning problem is known to be NP-hard. This paper investigates how to partition the vertex set of an undirected weighted graph into two disjoint subsets, such that the total vertex-weights of the two subsets are nearly equal, and the total weight of the edges connecting the two subsets is minimized. A heuristic algorithm is proposed to initialize an approximate bi-partition such that the total vertex-weight of each subset is close to that of the other. The proposed algorithm constructs a subset by selecting a group of neighbouring vertices with the highest gain from the original graph for inclusion into the subset. A customized tabu search is proposed to further refine the initial partition, which minimizes the communication cost and keeps partition balanced. Experimental results show that the proposed algorithms outperform the state-of-the-art on the public benchmarks, with the improvement of up to 79% for certain cases.

关键词： partitioning algorithms Approximation algorithms Heuristic algorithms Benchmark testing Software algorithms Joining processes Software

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Machine Learning for User partitioning and Phase Shifters Design in RIS-Aided NOMA Networks

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IEEE TRANSACTIONS ON COMMUNICATIONS 2021年第11期69卷 7414-7428页

作者： Yang, Zhong Liu, Yuanwei Chen, Yue Al-Dhahir, Naofal Queen Mary Univ London Sch Elect Engn & Comp Sci London E1 4NS England Univ Texas Dallas Dept Elect & Comp Engn Dallas TX 75080 USA

A novel reconfigurable intelligent surface (RIS) aided non-orthogonal multiple access (NOMA) downlink transmission framework is proposed. We formulate a long-term stochastic optimization problem that involves a joint optimization of NOMA user partitioning and RIS phase shifting, aiming at maximizing the sum data rate of the mobile users (MUs) in NOMA downlink networks. To solve the challenging joint optimization problem, we invoke a modified object migration automation (MOMA) algorithm to partition the users into equal-size clusters. To optimize the RIS phase shifting matrix, we propose a deep deterministic policy gradient (DDPG) algorithm to collaboratively control multiple reflecting elements (REs) of the RIS. Different from conventional training-then-testing processing, we consider a long-term self-adjusting learning model where the intelligent agent is capable of learning the optimal action for every given state through exploration and exploitation. Extensive numerical results demonstrate that: 1) The proposed RIS-aided NOMA downlink framework achieves enhanced sum data rate compared with the conventional orthogonal multiple access (OMA) framework. 2) The proposed DDPG algorithm is capable of learning a dynamic resource allocation policy in a long-term manner. 3) The performance of the proposed RIS-aided NOMA framework can be improved by increasing the granularity of the RIS phase shifts. The numerical results also show that increasing the number of reflecting elements (REs) is an efficient method to improve the sum data rate of the MUs.

关键词： NOMA Downlink Array signal processing Wireless communication Wireless networks Optimization Heuristic algorithms Machine learning partitioning algorithms wireless communication

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Fuzzy Space partitioning Based on Hyperplanes Defined by Eigenvectors for Takagi-Sugeno Fuzzy Model Identification

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2020年第6期67卷 5144-5153页

作者： Dovzan, Dejan Skrjanc, Igor Univ Ljubljana Fac Elect Engn SI-1000 Ljubljana Slovenia

This article presents a novel method for fuzzy space partitioning and the identification of Takagi-Sugeno fuzzy models. The novelty is in its region-splitting mechanism and membership function definition, which is based on hyperplanes. The proposed algorithm introduces a concept of principal component analysis to define the hyperplanes that split the problem space and uses the distances to these hyperplanes as metrics instead of center-oriented clusters. In contrast with many other methods, the presented method delivers reproducible results and has an easy tuning procedure. The performance is illustrated with analytical examples, benchmark problems from the literature, and real-process data. The obtained results are very promising;however, as with most learning methods, the results depend on the data distribution and input variable selection.

关键词： Takagi-Sugeno model Data models Computational modeling Clustering algorithms Principal component analysis Process control partitioning algorithms Eigen-hyperplane hierarchical fuzzy model principle component partitioning

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A GOMORY-HU CUT TREE-REPRESENTATION OF A NETLIST partitioning PROBLEM

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS 1990年第9期37卷 1133-1139页

作者： VANNELLI, A HADLEY, SW UNIV WATERLOO DEPT COMBINATOR & OPTIMIZATWATERLOO N2L 3G1ONTARIOCANADA

A VLSI design procedure is presented for finding netlist partitions. The method consists of approximating a netlist, which can be represented as a hypergraph, by an undirected graph with weighted edges. A Gomory-Hu cut tree allows one to generate netlist partitions for every pair of modules and estimate how far from optimality netlist cut is. Experimental results indicate that the netlist partitions are optimal or near-optical.< >

关键词： Tree graphs partitioning algorithms Very large scale integration Wires Printed circuits Microelectronics Councils Scholarships Joining processes Circuits and systems

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Logic Design partitioning for Stacked Power Domains

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2017年第11期25卷 3045-3056页

作者： Blutman, Kristof Fatemi, Hamed Kapoor, Ajay Kahng, Andrew B. Li, Jiajia de Gyvez, Jose Pineda NXP Semiconductors NL-5656 AG Eindhoven Netherlands Univ Calif San Diego Comp Sci Engn Dept La Jolla CA 92093 USA Univ Calif San Diego Elect & Comp Engn Dept La Jolla CA 92093 USA Univ Calif San Diego VLSI CAD Lab La Jolla CA 92093 USA

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which connects voltage domains in series, can effectively improve power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced currents between different domains across multiple operating scenarios. Furthermore, level shifter insertion, along with placement constraints imposed by power domain regions, can incur significant power and area penalties. To the best of our knowledge, no existing work performs subblock-level partitioning optimization for stacked-domain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced cross-domain current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floor plan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves an excellent current balance across stacked domains with less than 10% discrepancy, which results in up to more than 2x battery lifetime improvements.

关键词： Digital integrated circuits low-power optimization partitioning algorithms physical design power domains

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A Machine Learning-Powered Tier partitioning Methodology for Monolithic 3-D ICs

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2022年第11期41卷 4575-4586页

作者： Lu, Yi-Chen Pentapati, Sai Zhu, Lingjun Murali, Gauthaman Samadi, Kambiz Lim, Sung Kyu Georgia Inst Technol Dept Elect & Comp Engn Atlanta GA 30332 USA Qualcomm Technol Inc Res & Dev Dept San Diego CA 92121 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

Tier partitioning is one of the most critical stages in monolithic 3-D (M3D) integrated circuits (ICs) implementation flows. It transforms 2-D netlists into 3-D by performing tier assignment for each design instance, which directly impacts the power, performance, and area (PPA) metrics of final 3-D full-chip designs. However, the current state-of-the-art tier partitioning approach named bin-based min-cut algorithm has fundamental flaws that lead to severe drawbacks, such as timing degradation, 3-D routing overhead, and redundant monolithic intertier vias (MIVs) insertion. To overcome these issues, in this article, we propose TP-GNN, an unsupervised graph learning-based tier partitioning framework that utilizes graph neural networks (GNNs) and advanced machine learning (ML) techniques to perform tier partitioning. The proposed framework comprehends design- and technology-related parameters properly so that it is generalizable to various netlists and technologies. In addition, it can be integrated with any style of M3D design flows that require tier assignments of standard cells. In the experiments, we validate the proposed framework on seven industrial designs with two different fashions of M3D implementation flows: 1) partitioning-first (Snap3D) and 2) partitioning-last (Shrunk2D and Compact2D) flows. We demonstrate that our framework, TP-GNN, significantly improves the 3-D quality of results (QoR) across most testing designs in a large margin compared with the bin-based min-cut tier partitioning algorithm. Specifically, in OpenPiton, an RISC-V-based multicore system, we observe 27.4%, 7.7%, and 20.3% improvements in performance, wirelength, and energy-per-cycle, respectively. Finally, we perform a case study by applying the proposed framework to a heterogeneous M3D design flow, Pin3D, on a commercial CPU design and observe that TP-GNN reaches better partitioning solutions than the existing partitioning approaches for heterogeneous 3-D ICs.

关键词： Three-dimensional displays Integrated circuits partitioning algorithms Routing Timing Degradation Three-dimensional integrated circuits 3D integrated circuits (ICs) circuit partitioning physical design

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Capturing Spatial-Temporal Traffic Patterns: A Dynamic partitioning Strategy for Heterogeneous Traffic Networks

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IEEE ACCESS 2024年 12卷 131982-131992页

作者： Peng, Xianyue Wang, Hao Southeast Univ Sch Transportat Nanjing 211189 Peoples R China

Macroscopic fundamental diagram (MFD) has become a popular model used in developing network traffic controls for a roughly homogeneous traffic network, encounters limitations when applied to the inherently heterogeneous nature of real-world transportation networks, affecting its predictive accuracy and applicability. To address these challenges, this paper proposes a dynamic network partitioning strategy for heterogeneous traffic networks. We devise a spatial-temporal dual-form graph to accurately represent the road network's spatial-temporal traffic patterns. To solve the dynamic network partitioning problem, we employ a spectral theory technique known as RatioCut. Our evaluation of the partitioning methods' effectiveness relies on fitting performance to the MFD and network modularity as metrics. A case study set in Yangzhou, China, executed with the Simulation of Urban Mobility (SUMO), demonstrates the performance of our dynamic partitioning approach. The results highlight our method's ability to capture the spatial and temporal evolution of the congestion in the road network and cluster the heterogeneous network into multiple quasi-homogeneous regions. Moreover, it shows that speed is potentially a more accessible indicator for network partitioning as it performs similar to density and is easier to collect.

关键词： Roads Vehicle dynamics Traffic control Measurement partitioning algorithms Heuristic algorithms Clustering algorithms Spatiotemporal phenomena Network partitioning time-varying traffic spatial-temporal graph spectral clustering algorithm

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MaPart: An Efficient Multi-FPGA System-Aware Hypergraph partitioning Framework

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第10期43卷 3212-3225页

作者： Li, Benzheng Bi, Shunyang You, Hailong Qi, Zhongdong Guo, Guangxin Sun, Richard Zhang, Yuming Xidian Univ Sch Microelect Xian 710071 Shaanxi Peoples R China S2C Inc Emulat Dept Shenzhen 518055 Peoples R China

Multi-FPGA systems (MFSs) are increasingly important in addressing VLSI circuit emulation and prototyping. However, the limitations of I/O resources between Field programmable gate arrays (FPGAs) have driven the usage of TDM and FPGA-hop technologies, which complicate the partitioning problem. Consequently, designing a suitable partitioning process for MFS has emerged as a critical research question affecting overall system performance. This article proposes MaPart, a novel hypergraph partitioning framework, which aims to minimize the maximum path delay in MFS. MaPart combines binary search with a nonhop partitioner, TopoPart+, to minimize the maximum hop count during the partitioning process. Compared to previous nonhop partitioner, TopoPart+ provides enhanced problem-solving capabilities and achieves a remarkable 96% reduction in cut-size. Furthermore, the framework incorporates two successive local refinement algorithms that optimize the time-division multiplexing ratio, reduce total hop count, and alleviate congestion on critical paths. Additionally, MaPart includes a system-level router based on layered graphs, enabling flexible control of the hop count based on the timing criticality of each path. Experimental results demonstrate that the proposed framework achieves a significant 37% reduction in delay compared to baseline algorithms when evaluated using publicly available benchmarks.

关键词： Field programmable gate arrays Delays partitioning algorithms Time division multiplexing Routing Wires Logic gates Field programmable gate array (FPGA) hardware emulation partitioning timing driven routing

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A DYNAMIC partitioning SCHEME FOR PARALLEL TRANSIENT STABILITY ANALYSIS

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IEEE TRANSACTIONS ON POWER SYSTEMS 1992年第2期7卷 940-946页

作者： ZHU, N BOSE, A Arizona State University Tempe AZ USA

A dynamic partitioning scheme for a large power system is used to speed up the transient stability solution by utilizing different step sizes for the different portions. The partitioning and the different step sizes naturally lend themselves to a parallel implementation. In this paper, results are obtained by utilizing the successive over relaxation (SOR) Newton parallel algorithm on the Alliant FX/8, an eight processor parallel computer. For a 662 bus system, a total speedup, by partitioning and parallelizing, of 33.5 is obtained. Since parallelization by itself with 8 processors can produce a speedup of about 7, the partitioning scheme provides a speedup factor of about 5. The partitioning scheme in this paper is not specific to either the SOR-Newton algorithm or the Alliant machine, and its application to any other parallel method should result in a similar speedup.

关键词： Transient analysis Stability analysis Power system transients Power system dynamics Power system analysis computing Power system stability partitioning algorithms Parallel algorithms Concurrent computing Power system planning

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GATE MATRIX partitioning

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1989年第7期8卷 756-767页

作者： HUANG, S WING, O COLUMBIA UNIV DEPT ELECT ENGNNEW YORKNY 10027

An algorithm is presented which partitions a gate matrix into a number of matrices such that the total area and the aspect ratio of the circumscribing rectangle are improved. The algorithm is based on the min-cut algorithm. The gain function and the balance condition are redefined for the gate matrix problem. The time complexity of the algorithm is O(t)+O( mod N/sub I/ mod /sup 2/), where t is the number of gate-net intersections, and N/sub I/ the subset of nets that intersect long gates. A novel gate-sequencing algorithm, designed for assigning gates in the partitioned gate matrices simultaneously, is introduced. By using the simultaneous-gate-sequencing algorithm, the partitioned gate matrices are connected by sharing gates. Since the same column is used for a gate shared by adjacent matrices, the layout does not require extra routing area. Experimental results show significant improvement over the layout without partition. For the three examples used in a previous paper, the area reduction ranges from 11-41%. The aspect ratio improves from 2.63, 4.00, and 2.59 to 1.04, 1.22, and 1.28, respectively.< >

关键词： partitioning algorithms Routing Algorithm design and analysis

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