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Performance-driven MCM partitioning through an adaptive genetic algorithm

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1996年第4期4卷 434-444页

作者： Raman, S Patnaik, LM INDIAN INST SCI MICROPROCESSOR APPLICAT LABBANGALORE 560012KARNATAKAINDIA

We present a novel genetic algorithm-based partitioning scheme for multichip modules (MCM's) which integrates four performance constraints simultaneously: pin count, area, heat dissipation, and timing. We also present a similar partitioning algorithm based on evolutionary programming. Experimental studies demonstrate the superiority of these methods over deterministic Fiduccia-Mattheyes (FM) algorithm and simulated annealing (SA) technique. Our approach performs better than another genetic algorithm-based method recently reported. The adaptive change of crossover and mutation probabilities results in better convergence of the partitioning algorithm.

关键词： circuit layout CAD convergence of numerical methods genetic algorithms multichip modules probability adaptive genetic algorithm area constraint crossover probabilities evolutionary programming heat dissipation mutation probabilities partitioning algorith adaptive genetic algorithm Genetic Algorithm (GA) convergence of numerical methods circuit layout CAD Multichip modules HEAT DISSIPATION partitioning algorithms evolutionary algorithm

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AN EFFICIENT MULTILEVEL PLACEMENT TECHNIQUE USING HIERARCHICAL partitioning

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS 1992年第6期39卷 432-439页

作者： HAMADA, T CHENG, CK CHAU, PM UNIV CALIF SAN DIEGO DEPT ELECT & COMP ENGNLA JOLLACA 92093

Simulated annealing has been applied successfully to row-based placement problems. However, its requirement for computation time grows rapidly with the circuit size, making the simulated annealing placement of extra large circuits computationally expensive. We apply ratio cut hierarchical partitioning, which enables efficient multilevel simulated annealing. An over-lapping moving window scheme is used to compensate for the effect of partitioning on the placement quality. Through the use of hierarchical partitioning, the asymptotic run time complexity of this algorithm grows linearly as the function of the circuit size. The system is called placement by ratio cut partitioning (PRC). The results from several benchmark tests are presented demonstrating PRC to be 2.49% on average better than TimberWolfSC Ver5.6. Furthermore, the run time for PRC is 18.3% on average less than that required for TimberWolfSC Ver5.6 for large test cases with more than 2000 cells. For a 100-K sea of gates test case, a 7.09% reduction in total wire length over TimberWolfSC Ver5.6, and a 51.7% saving in CPU time, were achieved.

关键词： Simulated annealing Circuit simulation Computational modeling Partial response channels Testing Wire Central Processing Unit Processor scheduling Lapping partitioning algorithms

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Multilevel spectral hypergraph partitioning with arbitrary vertex sizes

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1999年第9期18卷 1389-1399页

作者： Zien, JY Schlag, MDF Chan, PK Univ Calif Santa Cruz Dept Comp Engn Santa Cruz CA 95064 USA

This paper presents a new spectral partitioning formulation which directly incorporates vertex size information by modifying the Laplacian of the graph. Modifying the Laplacian produces a generalized eigenvalue problem, which is reduced to the standard eigenvalue problem. Experiments show that the scaled ratio-cut costs of results on benchmarks with arbitrary vertex sizes improve by 22% when the eigenvectors of the Laplacian in the spectral partitioner KP are replaced by the eigenvectors of our modified Laplacian. The inability to handle vertex sizes in the spectral partitioning formulation has been a limitation in applying spectral partitioning in a multilevel setting. We investigate whether our new formulation effectively removes this limitation by combining it with a simple multilevel bottom-up clustering algorithm and an iterative improvement algorithm for partition refinement. Experiments show that in a multilevel setting where the spectral partitioner KP provides the initial partitions of the most contracted graph, using the modified Laplacian in place of the standard Laplacian is more efficient and more effective in the partitioning of graphs with arbitrary-size and unit-size vertices;average improvements of 17% and 18% are observed for graphs with arbitrary-size and unit size vertices, respectively. Comparisons with other ratio-cut based partitioners on hypergraphs with unit-size as well as arbitrary-size vertices, show that the multilevel spectral partitioner produces either better results or almost identical results more efficiently.

关键词： partitioning algorithms Iterative algorithms Laplace equations Eigenvalues and eigenfunctions Clustering algorithms Costs Logic arrays Circuits Performance analysis Databases

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A GENERAL-PURPOSE, MULTIPLE-WAY partitioning ALGORITHM

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1994年第12期13卷 1480-1488页

作者： YEH, CW CHENG, CK LIN, TTY UNIV CALIF SAN DIEGO DEPT ELECT & COMP ENGNLA JOLLACA 92093 UNIV CALIF SAN DIEGO DEPT COMP SCI & ENGNLA JOLLACA 92093

Multiple-way partitioning is an important extension of two-way partitioning as it provides a more natural and direct model for many partitioning applications. In this paper, we discuss several objective functions derived from such an extension and propose an iterative improvement algorithm to solve the multiple-way partitioning problem. The algorithm proceeds in three phases. The first phase employs a recursive ratio-cut scheme [11], [12] to group highly connected subcircuits into clusters. The second phase performs iterative improvement on the clustered circuit using a new net-based move model and a Primal-Dual refinement procedure. The third phase is the same as the second phase except that the iterative improvement is done on the original circuit. Experiments show good results in all tested cases compared to that proposed in [1].

关键词： partitioning algorithms Iterative algorithms Clustering algorithms Circuit testing Process design Timing Circuit simulation Simulated annealing Computer science Algorithm design and analysis

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A New Combinatorial Characteristic Parameter for Clustering-Based Traffic Network partitioning

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IEEE ACCESS 2019年 7卷 40175-40182页

作者： Liu, Duanyang Wang, Mengting Shen, Guojiang Zhejiang Univ Technol Coll Comp Sci & Technol Hangzhou 310023 Zhejiang Peoples R China

Traffic network partitioning is of great importance in regional coordinated traffic signal control in urban areas. Most partitioning algorithms only use a single traffic parameter to represent dynamic traffic information, which will lead to inaccurate results. Moreover, traditional clustering and heuristic partitioning algorithms are not practical in applications. Thus, in this paper, we first propose a new combinatorial characteristic parameter for clustering-based partitioning algorithm by using the Pearson correlation coefficient and data normalization. Then, we refer to the idea of "snake'' algorithm and use a linear programming model to obtain the exact partitioning result, and such algorithm avoids local optimum of heuristic algorithms. Finally, based on the real traffic data of a Chinese city, we conduct the experiments and verify the effectiveness of the new combinatorial parameter.

关键词： Intelligent transportation systems partitioning algorithms clustering methods correlation linear programming

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OPTIMUM KALMAN FILTER FOR LARGE-SCALE SYSTEMS USING partitioning APPROACH

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IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS 1976年第10期6卷 714-720页

作者： HASSAN, MF CNRS AUTOMATIQUE & ANAL SYST LAB F-31400 TOULOUSE FRANCE

The implementation of Kalman-Bucy linear filtering theory incurs computational difficulties especially in applications to large-dimensional systems. These difficulties can be overcome by using a partitioning technique. Based on this concept, a linear filtering method for large-scale systems is developed. In this method the interaction between the partioned subsystems is taken into consideration, and the resulting filter is the optimum linear minimum variance estimator. A numerical example is used to illustrate the approach.

关键词： Large-scale systems Nonlinear filters Kalman filters Maximum likelihood detection Rivers Covariance matrix partitioning algorithms Noise measurement Multiprocessing systems Filtering theory

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Random partitioning Forest for Point-Wise and Collective Anomaly Detection-Application to Network Intrusion Detection

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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2021年 16卷 2157-2172页

作者： Marteau, Pierre-Francois Univ Bretagne Sud IRISA UMR CNRS 6074 Campus Tohannic F-56000 Vannes France

In this paper, we propose DiFF-RF, an ensemble approach composed of random partitioning binary trees to detect point-wise and collective (as well as contextual) anomalies. Thanks to a distance-based paradigm used at the leaves of the trees, this semi-supervised approach solves a drawback that has been identified in the isolation forest (IF) algorithm. Moreover, taking into account the frequencies of visits in the leaves of the random trees allows to significantly improve the performance of DiFF-RF when considering the presence of collective anomalies. DiFF-RF is fairly easy to train, and good performance can be obtained by using a simple semi-supervised procedure to setup the extra hyper-parameter that is introduced. We first evaluate DiFF-RF on a synthetic data set to i) verify that the limitation of the IF algorithm is overcome, ii) demonstrate how collective anomalies are actually detected and iii) to analyze the effect of the meta-parameters it involves. We assess the DiFF-RF algorithm on a large set of datasets from the UCI repository, as well as four benchmarks related to network intrusion detection applications. Our experiments show that DiFF-RF almost systematically outperforms the IF algorithm and one of its extended variant, but also challenges the one-class SVM baseline, deep learning variational auto-encoder and ensemble of auto-encoder architectures. Finally, DiFF-RF is computationally efficient and can be easily parallelized on multi-core architectures.

关键词： Vegetation Anomaly detection Forestry Entropy Complexity theory Support vector machines partitioning algorithms Random forest machine learning semi-supervised learning anomaly detection intrusion detection NIDS

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Balanced Domain partitioning for Software Defined Networks

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IEEE ACCESS 2023年 11卷 6467-6476页

作者： Wu, Yuansheng Du, Junyi Ni, Dadong Southwest China Inst Elect Technol Chengdu 610036 Peoples R China

Software Defined Networking (SDN) has been widely adopted to enable the network programmability by decoupling the controller logic from the data plane. Domain partitioning is essential for SDN-enabled communication networks to partition the oversized network topology into controllable and administrative domains. Existing domain partitioning algorithms failed to take the connectivity, balance constraint, compactness, and traffic cohesion into consideration simultaneously which are required by SDN communications. This paper formulates the domain partitioning problem and proposed a novel balanced network partitioning (BaDoP) algorithm, which can enhance the balance of the partitioned domains, and optimize the compactness and traffic cohesion with connectivity constraint always guaranteed. BaDoP employs Bubble algorithm to find initial domain partitioning, and improves the domain partitioning iteratively by moving border nodes among the partitioned domains guided by the negative cycles or shortest paths on an auxiliary graph which is an abstract view of the current domain partitioning. The simulation results indicates that our BaDoP algorithm outperforms the previous algorithms and can achieve significant improvement for the balance of the partitioned domains.

关键词： partitioning algorithms Communication networks Clustering algorithms Software algorithms Network topology Software defined networking Iterative algorithms Auxiliary graph balanced domain partitioning compactness connectivity constraint negative cycle detection software-defined networking traffic cohesion

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Scalable, Multi-Constraint, Complex-Objective Graph partitioning

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2020年第12期31卷 2789-2801页

作者： Slota, George M. Root, Cameron Devine, Karen Madduri, Kamesh Rajamanickam, Sivasankaran Rensselaer Polytech Inst Dept Comp Sci Troy NY 12180 USA Sandia Natl Labs Scalable Algorithms Dept Albuquerque NM 87123 USA Penn State Univ Elect Engn & Comp Sci Dept University Pk PA 16810 USA

We introduce XtraPuLP, a distributed-memory graph partitioner designed to process irregular trillion-edge graphs. XtraPuLP is based on the scalable label propagation community detection technique, which has been demonstrated in various prior works as a viable means to produce high quality partitions of skewed and small-world graphs with minimal computation time. Our XtraPuLP implementation can also be generalized to compute partitions with an arbitrary number of constraints, and it can compute partitions with balanced communication load across all parts. On a collection of large sparse graphs, we show that XtraPuLP partitioning is considerably faster than state-of-the-art partitioning methods, while also demonstrating that XtraPuLP can produce partitions of real-world graphs with billion+ vertices and over a hundred billion edges in minutes. Additionally, we demonstrate XtraPuLP on a variety of applications, including large-scale graph analytics and sparse matrix-vector multiplication.

关键词： partitioning algorithms Scalability Sparse matrices Computational modeling Rats Indexes Social networking (online) Graph partitioning load balancing label propagation graph analysis

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partitioning and analysis of static digital CMOS circuits

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1997年第11期16卷 1292-1310页

作者： Hubner, U Vierhaus, HT Camposano, R Tech Univ Brandenburg Cottbus Germany Synopsys Inc Mountain View CA USA

Performance optimization of automatic test pattern generation (ATPG) algorithms has received considerable attention. While the application of high-performance algorithms is often limited to simple gates such as AND's, OR's, and XOR, the cell libraries of silicon vendors usually contain more sophisticated structures. To deal with this problem, we present a library independent algorithm for the partitioning and analysis of static digital CMOS circuits described at the snitch level. The algorithm recognizes inverters, NAND's, and NOR's. It also checks whether a partition can set ifs output to a high impedance state, thus being capable of partitioning large bus structures with tristate gates. Our approach supports existing ATPG algorithms at the gate level, Moreover, it allows a mixed-level approach for ATPG using detailed fault models at the switch level for whatever partitions it is necessary. Our implementation processes in the alder of 2000 transistors per second. This is for circuits containing combinational and sequential logic on a state-of-the-art workstation, We processed complete chips with up to 72 000 transistors, which is clearly adequate for practical purposes.

关键词： CMOS digital integrated circuits partitioning algorithms Automatic test pattern generation Switches Software libraries Optimization Silicon Algorithm design and analysis Switching circuits Inverters

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