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11th Euromicro Conference on Parallel, Distributed and Network-Based Processing

作者： Baños, R Gil, C Montoya, MG Ortega, J Univ Almeria Dept Arquitectura Computadores & Elect Almeria Spain

ISBN: (纸本)0769518753

,As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithm for circuit testing, logic minimization and simulation, HDL-based synthesis, etc. is currently a field of increasing research activity. In some of these applications the circuit partitioning problem occurs. That implies dividing a circuit into non-overlapping subcircuits while minimizing the number of cuts after the division and balancing the load associated to each one. Very effective heuristic algorithms have been developed in order to solve this problem, but it is unknown how good the partitions are since the problem is NP-complete. In these cases the use of parallel processing can be very useful. This paper describes a parallel evolutionary algorithm for circuit partitioning, where parallelism improves the solutions found by the corresponding sequential algorithm, which indeed is quite effective compared with other previously proposed procedures.

关键词： Application software Circuit testing Concurrent computing Evolutionary computation Logic circuits Logic testing Parallel algorithms Parallel processing partitioning algorithms Very large scale integration

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Performance-Driven Simultaneous partitioning and Routing for Multi-FPGA Systems 58

Performance-Driven Simultaneous Partitioning and Routing for...

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58th ACM/IEEE Design Automation Conference (DAC)

作者： Chen, Ming-Hung Chang, Yao-Wen Wang, Jun-Jie Natl Taiwan Univ Dept Elect Engn Taipei 10617 Taiwan Natl Taiwan Univ Grad Inst Elect Engn Taipei 10617 Taiwan

ISBN: (纸本)9781665432740

A multi-FPGA system consists of multiple FPGAs connected by physical wires, and a circuit is partitioned to fit each FPGA and routed on the system by such physical wires. Due to the limited numbers of input/output (I/O) pins in an FPGA, however, not all signals can be transmitted between FPGAs directly. Moreover, the routing resource may not be sufficient to accommodate many cross-FPGA signals from circuit partitioning. As a result, input/output time-division multiplexing (TDM) is introduced to send a group of cross-FPGA signals in a routing channel with a timing penalty. To optimize the performance of such a system, we shall develop a simultaneous partitioning and routing algorithm considering the timing penalty caused by I/O TDM. Considering the TDM delay penalty, we propose a simultaneous partitioning and routing algorithm to remedy the insufficiency of the two-stage flow of partitioning followed by routing. Our algorithm consists of two major steps: (1) a novel routing-aware partitioning framework to obtain an initial solution considering irregular, asymmetric connections, and (2) a partition-aware routing scheme to optimize routing in each partitioning pass. Experimental results show that our proposed algorithm can achieve better timing than the classical flow.

关键词： Design automation Wires Routing Time division multiplexing partitioning algorithms Delays Pins

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Revisiting the space-filling curves for storage, reordering and partitioning mesh based data in scientific computing

Revisiting the space-filling curves for storage, reordering ...

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20th International Conference on High Performance Computing (HiPC)

作者： Pavanakumar, M. Kaushik, K. N. CSIR Natl Aerosp Labs Computat & Theoret Fluid Dynam Div Bangalore Karnataka India

ISBN: (纸本)9781479907298

Graph based algorithms are widely used for unstructured mesh partitioning. They give rise to non-contiguous partitions optimized for minimum communication between partitions. Space-filling curves (SFC) on the other hand give better balanced partitions having higher communication cost than graphs. In this work, we show that SFC based algorithms are competitive to graph based methods, especially for I/O and compute intensive scientific applications. The basic idea used in this work is the SFC reordered storage in Hierarchical Data Format (HDF), which simplifies mesh partitioning, improves I/O bandwidth and at the same time provide cache friendly memory access. The ordering enables us to read the mesh entities as contiguous chunks using parallel I/O, which precludes the use of elaborate partitioning tools. We show comparisons of various partition quality metrics between partitions obtained from SFC and graph based methods for four types of unstructured meshes. The results show that SFC outperforms graph based partitioning in all the quality metrics except the communication volume. Finally, we show that storing the mesh entities using SFC leads to better cache locality without additional local reordering effort.

关键词： partitioning algorithms Bandwidth Synchronization Scalability Load management Laboratories

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MAGELLAN: Multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs 01

MAGELLAN: Multiway hardware-software partitioning and schedu...

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9th International Symposium on Hardware/Software Codesign (CODES 2001)

作者： Chatha, KS Vemuri, R Univ Cincinnati Dept ECECS Cincinnati OH 45221 USA

ISBN: (纸本)1581133642

The paper presents MAGELLAN, a heuristic technique for mapping hierarchical control-dataflow task graph specifications on heterogeneous architecture templates. The architecture can consist of multiple hardware and software processing elements as specified by the user The objective of the technique is to minimize the worst case latency of the task graph subject to the area constraints on the architecture. The technique uses an iterative approach consisting of closely linked hardware-software partitioner and scheduler Both the partitioner and scheduler operate on the task graph in a hierarchical top down manner. The technique optimizes deterministic loop constructs by applying clustering, unrolling and pipelining. The technique considers speculative execution for conditional constructs. The number of actual hardware/software implementations of a function in the task graph are also optimized by the technique. The effectiveness of the technique is demonstrated bit a case study of on image compression algorithm.

关键词： Delay Scheduling Counting circuits Coprocessors Communication system control partitioning algorithms Timing System buses Pipeline processing Feedback

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Efficient Hierarchical State Vector Simulation of Quantum Circuits via Acyclic Graph partitioning

Efficient Hierarchical State Vector Simulation of Quantum Ci...

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IEEE International Conference on Cluster Computing (CLUSTER)

作者： Fang, Bo Ozkaya, M. Yusuf Li, Ang Catalyurek, Umit V. Krishnamoorthy, Sriram Pacific Northwest Natl Lab Richland WA 99352 USA Amazon Web Serv Seattle WA USA Georgia Inst Technol Sch Computat Sci & Engn Atlanta GA 30332 USA

ISBN: (数字)9781665498562

ISBN: (纸本)9781665498562

Early but promising results in quantum computing have been enabled by the concurrent development of quantum algorithms, devices, and materials. Classical simulation of quantum programs has enabled the design and analysis of algorithms and implementation strategies targeting current and anticipated quantum device architectures. In this paper, we present a graph-based approach to achieving efficient quantum circuit simulation. Our approach involves partitioning the graph representation of a given quantum circuit into acyclic subgraphs/circuits that exhibit better data locality. Simulation of each sub-circuit is organized hierarchically, with the iterative construction and simulation of smaller state vectors, improving overall performance. Also, this partitioning reduces the number of passes through data, improving the total computation time. We present three partitioning strategies and observe that acyclic graph partitioning typically results in the best time-to-solution. In contrast, other strategies reduce the partitioning time at the expense of potentially increased simulation times. Experimental evaluation demonstrates the effectiveness of our approach.

关键词： Computational modeling Graphics processing units Computer architecture Cluster computing Supercomputers partitioning algorithms Computational efficiency

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A Comparative Analysis of Spatial partitioning Methods for Large-scale, Real-time Crowd Simulation 21

A Comparative Analysis of Spatial Partitioning Methods for L...

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21st International Conference in Central Europe on Computer Graphics, Visualization and Computer Vision

作者： Li, Bo Mukundan, Ramakrishnan Univ Canterbury Christchurch New Zealand

ISBN: (纸本)9788086943756

Acceleration algorithms involving spatial partitioning methods are extensively used in crowd simulation for real-time collision avoidance. Memory and update costs become increasingly important as the crowd size becomes large. The paper presents a detailed analysis of the effectiveness of spatial subdivision data structures, specifically for large-scale crowd simulation. The results demonstrate that a regular grid data structure combined with an extended oriented bounding volume for crowd members can facilitate efficient updates necessary for real-time performance.

关键词： Crowd simulation crowd animation partitioning algorithms collision detection subdivision data structures bounding volumes

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Searching for nearest neighbors with a dense space partitioning

Searching for nearest neighbors with a dense space partition...

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IEEE International Conference on Image Processing, ICIP 2015

作者： Nguyen, Tuan Anh Matsui, Yusuke Yamasaki, Toshihiko Aizawa, Kiyoharu University of Tokyo Japan

ISBN: (纸本)9781479983391

Product quantization based approximate nearest neighbor search with the use of inverted index structures have recently received increasing attention. In this paper, we propose a new inverted index structure for searching nearest neighbors in very large datasets of high dimensional data. For data indexing, our proposed method creates a dense space partitioning using multiple centroids based assigning, which generates shorter candidate lists and improves the search speed. Our experiments with a dataset of one billion SIFT features show that while achieving higher accuracy, our method demonstrates better performances on search speed compared to IV-FADC, the conventional product quantization based inverted index structure. © 2015 IEEE.

关键词： Estimation Indexing Nearest neighbor searches partitioning algorithms Quantization (signal) computer vision image retrieval inverted index nearest neighbor search product quantization

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A partitioning GPU-based Algorithm for Processing the k Nearest-Neighbor Query 20

A Partitioning GPU-based Algorithm for Processing the k Near...

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12th International Conference on Management of Digital EcoSystems

作者： Velentzas, Polychronis Vassilakopoulos, Michael Corral, Antonio Univ Thessaly Dept Elect & Comp Engn Data Structuring & Engn Lab Volos Greece Univ Almeria Dept Informat Almeria Spain

ISBN: (纸本)9781450381154

The kappa Nearest-Neighbor (kappa-NN) query is a common spatial query that appears in several big data applications. Typically, GPU devices have much larger numbers of processing cores than CPUs and faster device memory than main memory accessed by CPUs, thus, providing higher computing power. We propose and implement a new GPU-based partitioning algorithm for the kappa-NN query, using the CUDA runtime API. Due to partitioning, this algorithm avoids calculating distances for the whole dataset. Using synthetic and real datasets, we present an extensive experimental performance comparison against six existing algorithms. These algorithms are based on calculating distances for the whole in-memory dataset. This comparison shows that the new algorithm excels in all the conducted experiments and outperforms these six algorithms.

关键词： k Nearest-Neighbor Query GPU algorithms Spatial query partitioning algorithms Parallel computing

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FPART: A multi-way FPGA partitioning procedure based on the improved FM algorithm

FPART: A multi-way FPGA partitioning procedure based on the ...

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3rd Meeting of the Asia and South-Pacific Design Automation Conference (ASP-DAC 98) / EDA Techno Fair 98

作者： Zhou, RZ Tong, JR Tang, PS Fudan Univ Dept Elect Engn Shanghai 200433 Peoples R China

ISBN: (纸本)0780344251

In this paper, a multi-way FPGA partitioning procedure FPART is introduced. The objective function of this procedure is to reduce the number of FPGA devices and the IOB utilization. An improved min-span FM bi-partitioning algorithm on the basis of an advanced gain model is adopted as the fundamental method, and three modules: init-part, optimize, and merge are combined in FPART to approach better results. After initial partitioning, the procedure optimizes the subsets to reduce the total span of cutset and then merges some subsets by removing the cells in them. Experimental results with MCNC'93 benchmarks show that FPART is fast and efficient.

关键词： Field programmable gate arrays partitioning algorithms Costs Very large scale integration Libraries Research and development Circuit testing Delay Size control

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Weighted Cluster Ensemble Based on Partition Relevance Analysis With Reduction Step

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IEEE ACCESS 2020年 8卷 113720-113736页

作者： Ilc, Nejc Univ Ljubljana Fac Comp & Informat Sci Ljubljana 1000 Slovenia

Over the last decade, the advent of the cluster ensemble framework has enabled more accurate and robust data analysis than traditional single clustering algorithms. The improved clustering of microarray data has had a particularly strong impact in the fields of genomics and medicine. However, when we bring several ensemble members together to form a consensus, low-quality data partitions can seriously compromise the final solution. One way to overcome this problem is the weighted cluster ensemble approach based on Partition Relevance Analysis (PRA), which uses internal cluster validity indices to evaluate and weight the ensemble members before the fusion. Unfortunately, the selection of appropriate validation indices for given data is far from trivial. In this paper, we propose an additional step in PRA that reduces the size of the committee of cluster validation indices. It does so by eliminating redundant and noisy indices using data dimensionality reduction methods. Our extension works in an unsupervised way, minimizing the amount of user intervention and required expert knowledge. We adapted three conventional consensus functions based on the principle of evidence accumulation to work with PRA weights. We demonstrate the advantages of the proposed reduction step of PRA based on extensive experiments with 25 gene expression and 15 non-genetic real-world datasets, where we compared 15 consensus functions. The source code is available at https://***/nejci/PRAr.

关键词： Clustering algorithms partitioning algorithms Feature extraction Indexes Gene expression Robustness Cluster analysis cluster validity index dimensionality reduction ensemble learning feature extraction feature selection gene expression weighted ensemble

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