We consider a pipeline array of processors where local communications are based on a producer-consumer mechanism. It is assumed that any processor contains a buffer of size one, and that the cycle-time of any processo...
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We consider a pipeline array of processors where local communications are based on a producer-consumer mechanism. It is assumed that any processor contains a buffer of size one, and that the cycle-time of any processor is a periodic sequence of period s ( j ), s ( j + 1),..., s ( n ),..., s ( j − 1), where s is a fixed permutation of 1,2,..., n , and j may vary from one processor to another. We give upper and lower bounds for the performance of the system.
Cellular arrays have been the topic of interest in computer arithmetic and architecture for the last four decades. In this letter, an overall quantum-dot cellular automata (QCA) design for a generalized pipeline cellu...
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Cellular arrays have been the topic of interest in computer arithmetic and architecture for the last four decades. In this letter, an overall quantum-dot cellular automata (QCA) design for a generalized pipeline cellular array is presented. QCA is one of the promising emerging nanotechnologies that are being considered as possible alternatives to complementary metal-oxide semiconductor technology due to the physical limitations of CMOS. The QCA designs for arithmetic cell and control cell used in the pipeline array are discussed in detail. The equivalent majority logic networks to these cells are generated using the best existing majority logic synthesis method in order to obtain the optimal majority networks which require fewer QCA cells and clock zones compared to other synthesis methods. The proposed array can perform all the basic arithmetic operations such as squaring, square rooting, multiplication, division, etc., which could be quite valuable in considering future large-scale QCA designs.
A VLSI implementation of a unified algorithm with the capability of computing all the common arithmetic operations, including division, square rooting etc. and most trigonometric functions, is described. The processor...
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A VLSI implementation of a unified algorithm with the capability of computing all the common arithmetic operations, including division, square rooting etc. and most trigonometric functions, is described. The processor has been designed in 3 μm CMOS technology such that when organised in a pipeline array it can achieve computation rates equivalent to 50 ns, suitable for most real-time signal and image processing applications.
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