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Africanus I. Scalable, distributed and efficient radio data processing with Dask-MS and Codex Africanus

ASTRONOMY AND computing 2025年 52卷

作者： Perkins, S. J. Kenyon, J. S. Andati, L. A. L. Bester, H. L. Smirnov, O. M. Hugo, B. V. South African Radio Astron Observ SARAO Cape Town South Africa Rhodes Univ Ctr Radio Astron Tech & Technol RATT Dept Phys & Elect Makhanda EC South Africa Natl Inst Astrophys INAF IRA Inst Radioastron Bologna Italy

The physical configuration of new radio interferometers such as MeerKAT, SKA, ngVLA and DSA-2000 informs the development of software in two important areas. Firstly, tractably processing the sheer quantity of data produced by new instruments necessitates subdivision and processing on multiple nodes. Secondly, the sensitivity inherent in modern instruments due to improved engineering practices and greater data quantities necessitates the development of new techniques to capitalize on the enhanced sensitivity of modern interferometers. This produces a critical tension in radio astronomy software development: a fully optimized pipeline is desirable for producing science products in a tractable amount of time, but the design requirements for such a pipeline are unlikely to be understood upfront in the context of artefacts unveiled by greater instrument sensitivity. Therefore, new techniques must continuously be developed to address these artefacts and integrated into a full pipeline. As Knuth reminds us, "Premature optimization is the root of all evil". This necessitates a fundamental trade-off between a trifecta of (1) performant code (2) flexibility and (3) ease-of-development. At one end of the spectrum, rigid design requirements are unlikely to capture the full scope of the problem, while throw-away research code is unsuitable for production use. This work proposes a framework for the development of radio astronomy techniques within the above trifecta. In doing so, we favour flexibility and ease-of-development over performance, but this does not necessarily mean that the software developed within this framework is slow. Practically this translates to using data formats and software from the Open Source Community. For example, by using NuMPy arrays and/or PANDAS dataframes, a plethora of algorithms immediately become available to the scientific developer. Focusing on performance, the breakdown of Moore's Law in the 2010s and the resultant growth of both multi-core an

关键词： Standards Techniques Interferometric Computer systems organization pipeline computing Software and its engineering Data flow architectures Cloud computing Interoperability Scheduling Distributed systems organizing principles Multithreading

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PIPECIM: Energy-Efficient pipelined computing-in-Memory Computation Engine With Sparsity-Aware Technique

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第2期33卷 525-536页

作者： Wang, Yuanbo Chang, Liang Wang, Jingke Zhao, Pan Zeng, Jiahao Zhao, Xin Hao, Wuyang Zhou, Liang Tan, Haining Han, Yinhe Zhou, Jun Univ Elect Sci & Technol China Sch Informat & Commun Engn Chengdu 611731 Peoples R China Chinese Acad Sci Inst Comp Technol Beijing 100190 Peoples R China

computing-in-memory (CIM) architecture has become a promising solution to improve the parallelism of the multiply-and-accumulation (MAC) operation for artificial intelligence (AI) processors. Recently, revived CIM engine partly relieves the memory wall issue by integrating computation in/with the memory. However, current CIM solutions still require large data movements with the increase of the practical neural network model and massive input data. Previous CIM works only considered computation without concern for the memory attribute, leading to a low memory computing ratio. This article presents a static-random access-memory (SRAM)-based digital CIM macro supporting pipeline mode and computation-memory-aware technique to improve the memory computing ratio. We develop a novel weight driver with fine-grained ping-pong operation, avoiding the computation stall caused by weight update. Based on our evaluation, the peak energy efficiency is 19.78 TOPS/W at the 22-nm technology node, 8-bit width, and 50% sparsity of the input feature map.

关键词： In-memory computing Neural networks Common Information Model (computing) Energy efficiency Computer architecture pipelines Program processors Indexes Convolution Engines computing-in-memory (CIM) digital circuit low power multiply-and-accumulator pipeline computing

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pipeline Architecture for N=K*2^L Bit Modular ALU: Case Study between Current Generation computing and Vedic computing 6

Pipeline Architecture for N=K*2<SUP>L</SUP> Bit Modular ALU:...

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6th International Conference for Convergence in Technology (I2CT)

作者： Chiranjeevi, G. N. Kulkarni, Subhash PESIT Dept Elect & Commun Engn Bangalore South Campus Bangalore 560100 Karnataka India Visvesvaraya Technol Univ Belagavi Karnataka India

ISBN: (纸本)9781728188768

This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using '2L' as base modules using 'K' modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

关键词： modular architecture Vedic computing arithmetic algorithms of ALU pipeline computing digital signal processing

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A Controllable pipeline Framework of Block Ciphers on GPU for Streaming Data

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IEEE ACCESS 2023年 11卷 93980-93993页

作者： Xiao, Chaoen Zhao, Guangyue Zhang, Lei Ding, Ding Beijing Elect Sci & Technol Inst Dept Elect & Commun Engn Beijing 100070 Peoples R China Beijing Elect Sci & Technol Inst Dept Cyberspace Secur Beijing 100070 Peoples R China

With the application and development of real-time multimedia information technology such as online meetings and short videos, the demand for secure transmission of streaming media data based on high throughput and low latency has increased significantly. Since servers must encrypt large amounts of data in real-time without compromising their service capabilities, Graphic Processing Units (GPUs) are considered the best candidates for cryptographic accelerators to handle large amounts of data in this situation. For the characteristics of streaming data, this paper proposes a GPU-based controllable pipelined encryption framework, which guarantees security during streaming data transmission while satisfying the requirements of high throughput and low latency. Firstly, in order to make the CPU in the traditional heterogeneous system understand the intermediate state of the GPU's operation in real-time, this paper adopts the cyclic checkpoint mechanism to realize the interrupt control;secondly, real-time signal feedback between the host and the device each other during the execution of the kernel function is realized by real-time monitoring and other modules;through the above ways, the CPU-GPU pipeline control framework is realized. Finally, based on AES and SM4 encryption algorithms, this paper designs and realizes the pipeline encryption and decryption process of streaming data based on CUDA in Python environment, and verifies the group automation pipeline framework based on interrupt monitoring and controlling through experiments;and under the condition of using 5 threads grouping, the data throughput rate reaches 1.01Gbps, which has a high throughput rate.

关键词： Graphics processing units Ciphers Encryption Throughput Cryptography pipelines Graphic processing units (GPUs) pipeline computing block cipher CUDA

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Recovery Strategies for Streaming Media Service in a Cluster-Based VOD Server with a Fault Node

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2009年第2期37卷 175-194页

作者： Lee, Joahyoung Jung, Inbum Kangwon Natl Univ Dept Comp Sci & Engn Chunchon 200701 South Korea

Due to the economic cost and good scalability, cluster-based server architecture is used for VOD services. This server consists of a front-end node and multiple backend nodes. In this server architecture, backend nodes are added simply to support large-scale on-demand clients. However, as the number of backend nodes increases, the possibility of backend node failure also increases. A backend node fault not only degrades the quality of serviced streaming media but also decreases the number of streams supported in the VOD server. For successful VOD service, even if a backend node enters a fault state, the streaming service in progress should be re-continued after a short recovery time. As the recovery strategy, when legacy RAID methods are applied to cluster-based VOD servers, the excessive internal network traffic between the backend nodes causes performance degradation. In addition, the backend nodes demonstrate inefficient CPU utilization for the recovery process. In this paper, to address these problems, a new fault recovery strategy is proposed based on the pipeline computing concept. The proposed method not only distributes the network traffic generated from the recovery operations but also makes efficient use of the CPU time available in the backend nodes. Based on these advantages, even if the cluster-based server has a backend node that fails, the proposed method provides more QoS streams compared to the existing recovery method. In addition, since the proposed method needs a very short recovery time, the streaming services in progress are sustained without degradation of media quality.

关键词： Cluster server Recovery pipeline computing Streaming service

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Principles and construction of MSD adder in ternary optical computer

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Science China(Information Sciences) 2010年第11期53卷 2159-2168页

作者： JIN Yi1, SHEN YunFu1, PENG JunJie1, XU ShiYi1, DING GuangTai1, YUE DongJian1 & YOU HaiHang2 1School of Computer Engineering & Science, Shanghai University, Shanghai, 200072 China 2National Institute for Computational Sciences, Oak Ridge, TN37831, USA School of Computer Engineering & Science Shanghai University Shanghai China National Institute for Computational Sciences Oak Ridge USA

The two remarkable features of ternary values and a massive unit with thousands bits of parallel computation will make the ternary optical computer (TOC) with modified signed-digit (MSD) adder more powerful and e?cient than ever before for numerical calculations. Based on the decrease-radix design presented previously, a TOC can satisfy either a user requiring huge capacity for data calculations or one with a moderate amount of data, if it is equipped with a prepared adder. Furthermore, with the application of pipelined operations and the proposed data editing technique, the e?ciency of the prepared adder can be greatly improved, so that each calculated result can be obtained almost within one clock cycle. It is hopeful that by employing a MSD adder, users will be able to enter a new dimension with the creation of a new multiplier, new divider, as well as new matrix operator in a TOC in the near future.

关键词： ternary optical computer (TOC) modified signed-digit (MSD) adder pipeline computing data editing technique

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Automatic High-Level Programs Mapping onto Programmable Architectures 13th

Automatic High-Level Programs Mapping onto Programmable Arch...

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13th International Conference on Parallel computing Technologies (PaCT)

作者： Steinberg, Boris Ya Dubrov, Denis V. Mikhailuts, Yury Roshal, Alexander S. Steinberg, Roman B. Southern Fed Univ Rostov Na Donu Russia

ISBN: (纸本)9783319219097;9783319219080

Atechnique for automatic high-level C program mapping onto compute systems with programmable pipeline architecture is presented in this article. An example of such a system could be a CPU with an FPGA accelerator or the corresponding system on a chip. The mapping is implemented on the base of Optimizing Parallelizing System (***) and C2HDL converter from C to the hardware description language (VHDL). HDL code generating from OPS internal representation would allow to utilize the user dialog to generate a family of equivalent chips, from which the user could select the most suitable one for various characteristics. The development of the current work would allow to create for the first time the C language compiler for the programmable pipeline architecture.

关键词： Reconfigurable computing pipeline computing High-level synthesis Parallelizing compiler High level internal representation HDL FPGA

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pipelined computing-in-Memory Macro with Computation-Memory Aware Technique

Pipelined Computing-in-Memory Macro with Computation-Memory ...

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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Chang, Liang Zhao, Pan Zhou, Jun Univ Elect Sci & Technol China Chengdu Peoples R China

ISBN: (纸本)9781665450737

computing-in-Memory (CIM) architecture is suitable for artificial intelligent accelerators, where frequent data movements are required between computation and memory units. CIM-based processing engine reduces redundant data interaction by integrated computation in/with memory and has become a promising candidate to alternate traditional multiply-and-accumulator (MAC). However, most of the previous CIM macros only considered computation without concern for the memory attribute, leading to a low memory computing ratio. This paper presents an SRAM-based digital CIM macro supporting pipeline mode and computation-memory aware technique to improve the ratio of memory-computation. We develop a novel weight driver with fine-grained ping-pong operation, avoiding the computation halt caused by weight updating. Based on our evaluation, the peak energy efficiency is 19.78TOPS/W at 22 nm technology node, 8-bit width, and 50% sparsity of input feature map.

关键词： computing-in-Memory Digital Circuit Low power pipeline computing Multiply-and-accumulator

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Developing a High-Level Language Compiler for a Computer with Programmable Architecture 16

Developing a High-Level Language Compiler for a Computer wit...

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12th Central and Eastern European Software Engineering Conference in Russia

作者： Steinberg, Boris Ya. Bugliy, Anton P. Dubrov, Denis V. Mikhailuts, Yury V. Steinberg, Roman B. Southern Fed Univ II Vorovich Inst Math Mech & Comp Sci Milchakov St 8a Rostov Na Donu 344090 Russia

ISBN: (纸本)9781450348843

The following work describes a project development of the C compiler for computing systems with programmable architectures. The compiler has been implemented on the base of OPS (Optimizing Parallelizing System, http://***) and a converter of C language into VHDL (C2HDL). An example of the compiler use has been presented in the article.

关键词： Reconfigurable computations pipeline computing high-level synthesis parallelizing compiler high-level internal representation HDL FPGA MI

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WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool

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SOFTWAREX 2022年 18卷

作者： Mariotti, Gianfranco Giorgi, Roberto Univ Siena Dept Informat Engn & Math Via Roma 56 I-53100 Siena Italy

WebRISC-V is a web-based education-oriented tool, which permits the investigation of the pipelined execution of assembly programs according to the RV32IM and RV64IM specifications (32-bit or 64-bit RISC-V processor). The tool permits to evaluate and understand slow-downs in the execution due to pipeline stalls and further investigate the internal state of the pipeline architectural blocks (e.g., registers, memory, multiplexers, ALU). The pipeline concept is illustrated in the vast majority of university courses in Computer Architecture, since it is the well established standard for implementing high-performance processors. However, the impact of pipelined execution is often underestimated or even unknown, whilst it represents a very important source for the speed-up of programs. Several similar tools exist and are publicly available, but WebRISC-V is currently the first one that can be executed directly in a web-browser while displaying the cycle-by-cycle detailed pipeline execution for a RISC-V processor. This paper describes WebRISC-V, compares it against other similar available tools and presents its features. An example of usage for investigating the pipeline with the support of an automatically generated pipeline diagram is provided. (C) 2022 The Author(s). Published by Elsevier B.V.

关键词： Simulation environments Interactive learning environments Computer architectures pipeline computing

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