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2012 International Conference on Signals and Electronic Systems (ICSES)

作者： Petrovsky, Alexey Stankevich, Andrew Petrovskyi, Alexander Belarusian State Univ Informat & Radioelect Dept Comp Engn Minsk BELARUS

ISBN: (纸本)9781467317092

This paper presents the implementation on the FPGA module CABAC decoder for h.264. The organization of the computational process is based on the pipe-line architecture that allows to simultaneously decoding multiple bins. This scheme is implemented on FPGA with clock frequency equal 96MHz and provides decoding of one bin per cycle.

关键词： Field programmable gate arrays pipeline processing CABAC clock frequency DECODING decoders

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Flexible hardware approach to multi-core time-predictable systems design based on the interleaved pipeline processing

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IET CIRCUITS DEVICES & SYSTEMS 2020年第5期14卷 648-659页

作者： Antolak, Ernest Pulka, Andrzej Silesian Tech Univ Fac Automat Control Elect & Comp Sci Ul Akad 16 PL-44100 Gliwice Poland

The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8-12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

关键词： reduced instruction set computing multi-threading pipeline processing field programmable gate arrays processor scheduling flip-flops logic design multiprocessing systems interleaved pipeline processing hardware-based approach time-predictable electronic embedded systems reconfigurable system architectures ARM-like RISC solutions hardware threads replicated register files deadline controlling mechanism memory system flexible hardware approach multicore time-predictable systems design reconfigurable pipelining Virtex-7 FPGA platforms

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Fast calculation using parallel processing and pipeline processing in power system analysis

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ELECTRICAL ENGINEERING IN JAPAN 1996年第5期116卷 85-96页

作者： Oda, Y Oyama, T YOKOHAMA NATL UNIV YOKOHAMAKANAGAWA 240JAPAN

This paper presents an application of parallel processing and pipeline processing to power system analysis. The system matrix is transformed to a bordered block diagonal form (BBDF) matrix for effective utilization of the processors. After LU factorization, subnetworks organize sparse matrices and the boundary network organizes a full matrix. First, a parallel processing technique is used to calculate subnetworks. Then, as pipeline processing is applied, inverse matrix of the boundary network is multiplied. The proposed method is made operational on a parallel computing system including a pipeline processor. A consideration on the transient stability analysis using the proposed method also is presented at the end of this paper.

关键词： parallel processing pipeline processing BBDF matrix transient stability analysis

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An Efficiency pipeline processing Approach for OpenFlow Switch 41

An Efficiency Pipeline Processing Approach for OpenFlow Swit...

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41st IEEE Conference on Local Computer Networks (LCN)

作者： Wu, Zhenwei Jiang, Yong Yang, Shu Tsinghua Univ Grad Sch Shenzhen Shenzhen Peoples R China Tsinghua Univ Tsinghua Natl Lab Informat Sci & Technol TNList Beijing Peoples R China Tsinghua Univ Dept Comp Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781509020546

One primary component of OpenFlow switches is a pipeline of flow tables. Flows are directed through the pipeline by looking up a matched rule in each table. Sequentially, Packet matching starts at table 0 and continues to additional tables of the pipeline if necessary. The lookup stops when one flow entry is matched or the end of pipeline is reached. Though effective, this manner of processing is not efficient when popular rules are installed in back tables. If frequently matched rules appear earlier in the pipeline, the procedure of lookup and comparison can be improved. Unfortunately, a simple sorting algorithm is not feasible. In this paper, we formalize the problem of reducing lookup times, which is proven to be NP-hard. A heuristic approach, MILE(migrating flow rules), is proposed to minimize the average number of lookups. Experimental results show that MILE is able to reduce table lookups by 50%.

关键词： SDN OpenFlow Switch pipeline processing

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A Circular pipeline processing Based Deterministic Parallel Test Pattern Generator

A Circular Pipeline Processing Based Deterministic Parallel ...

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IEEE International Test Conference (ITC)

作者： Yeh, Kuen-Wei Huang, Jiun-Lang Chao, Hao-Jan Wang, Laung-Terng Natl Taiwan Univ Grad Inst Elect Engn Taipei Taiwan Natl Taiwan Univ Dept Elect Engn Taipei Taiwan SynTest Technol Inc Sunnyvale CA USA

ISBN: (纸本)9781479908592

Parallel programming is an attractive solution to accelerate test pattern generation (TPG);however, the associated non-determinism often leads to non-reproducible test pattern sets. In this paper, the circular pipeline processing (CPP) principle is proposed to facilitate deterministic parallel TPG. CPP preserves the task processing orders that are necessary to ensure TPG determinism with low inter-thread synchronization overhead. Based on CPP, a deterministic parallel test pattern generator is developed;it guarantees to produce the same test pattern set regardless of the thread timing and the thread count. Experimental results on benchmark circuits show that the proposed test pattern generator exhibits close-to-linear speedup for at least up to 12 threads.

关键词： automatic test pattern generation benchmark testing parallel programming pipeline processing

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High-performance pipeline processing for ASKAP 2

High-performance pipeline processing for ASKAP

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2nd URSI Atlantic Radio Science Meeting (AT-RASC)

作者： Whiting, M. Ord, S. M. Mitchell, D. Voronkov, M. Guzman, J. C. CSIRO Astron & Space Sci Sydney NSW Australia

ISBN: (纸本)9789082598735

The Australian Square Kilometre Array Pathfinder is a radio-synthesis telescope, featuring thirty-six 12m dishes equipped with phased-array-feed receivers. These provide a wide, 30 square degree instantaneous field-of-view by forming up to 36 separate dual-polarisation beams at once. This results in a high data rate: 70 TB of correlated visibilities in an 8 hour observation, requiring high-performance calibration & imaging pipelines. The ASKAPsoft package has been developed specifically for meeting this challenging problem. Particular design decisions in the imaging algorithms, and the framework under which they run, have been made to meet processing requirements on memory and run-time, and scientific requirements. The ASKAPsoft software is deployed on the Cray XC30 “Galaxy” supercomputer at the Pawsey Supercomputing Centre in Perth, Western Australia. Since ASKAP will be primarily a survey telescope, these processing pipelines must run in near-realtime, commencing once an observation is completed and completing in time to process the next. All calibration and imaging is done within these pipelines, followed by the formation of astronomical catalogues, and the resulting data products (calibrated visibilities, images, cubes, and catalogues) are stored in the CSIRO ASKAP Science Data Archive. ASKAP is currently conducting its Early Science program with an array of 12 PAF equipped antennas. This is a series of small surveys that allow the ASKAP science teams to address key scientific questions in the lead-up to the full-scale Survey Science Projects with the full 36-antenna array, and at the same time contribute to the development of ASKAP operations and processing. We will present examples of these products such as a 31 square degree, continuum image of the field surrounding NGC 7232. Datasets from this and related observations are available now through CASDA.

关键词： pipeline processing Telescopes Arrays Australia Imaging Phased arrays Calibration

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pipeline processing of Multi-Way Queries in Shared-Memory Systems

Pipeline Processing of Multi-Way Queries in Shared-Memory Sy...

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International Conference on Parallel processing (ICPP)

作者： Kian-Lee TAN Hongjun LU Department of Information Systems and Computer Science National University of Singapore Singapore

This paper explores the pipeline processing of multi-way join queries using hash-based join algorithm. The basic approach that has been adopted in the literature is: "split" the join tree into segments and for each segment, split each base rela tion into buckets and pipeline the segment using the buckets. The effectiveness of the approach depends on two closely related factors - the number of buckets and the number of segments. We investigate how varying these factors may affect the system performance. Two greedy heuristics, proposed to generate query evalua tion plans with "optimal" pipeline length, are shown to perform best in most cases.

关键词： pipeline processing Parallel processing System performance Relational databases Cost function Samarium Information systems Computer science Internet Delay

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Experimental research of passive bistatic radar based on pipeline processing

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JOURNAL OF ENGINEERING-JOE 2019年第20期2019卷 7157-7160页

作者： Zheng, Guangyong Wang, Huabing Li, TingPeng State Key Lab Complex Electromagnet Environm Effe Luoyang Peoples R China

For passive bistatic radar (PBR), it is convenient to use software method to realise the signal processing. However, because of the huge amount of data computing, it is difficult to achieve the real-time signal processing by software method only with server that uses CPU for calculation. To solve the problem, the PBR signal processing method with multi-CPUs based on pipeline processing is studied. The key point of the method is to improve the parallelism of the signal processing algorithm and to use all the CPU cores efficiently for parallel computing. The whole PBR signal processing is divided into several steps, such as clutter cancellation, correlation processing, CFAR detection and so on, and each step employs different CPU resources that contain many cores. The data processed in each steps is also divided into several pieces to fully use all the CPU cores. At last, the signal processing in software for digital television terrestrial broadcasting (DTTB) signal is achieved based on the method. The experiment is carried out to verify the method. In the experiment, the whole signal processing time for DTTB signal is much less than the time of signal to be processed, and the signal processing output is continuous.

关键词： digital video broadcasting television broadcasting passive radar pipeline processing radar signal processing microprocessor chips radar computing signal processing time DTTB signal signal processing output passive bistatic radar pipeline processing software method data computing PBR signal processing method CPU cores parallel computing correlation processing digital television terrestrial broadcasting signal CPU resources real-time signal processing algorithm

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UMP-PerComp: A Ubiquitous Multiprocessor Network-Based pipeline processing Framework for Pervasive Computing Environments

UMP-PerComp: A Ubiquitous Multiprocessor Network-Based Pipel...

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International Conference on Advanced Information Networking and Applications (AINA)

作者： M. Kubo Baoliu Ye A. Shinozaki T. Nakatomi Minyi Guo Future Creation Laboratory Olympus Corporation Shinjuku Tokyo Japan Department of Computer Software University of Aizu Fukushima Japan State Key Laboratory for Novel Software and Technology Nanjing University Nanjing China

Pervasive computing provides an attractive vision for the future of computing where contextual intelligent services will be available anywhere at any time. However, how to integrate distributed resources existed among heterogeneous devices to build pervasive applications that can constantly adapt to the highly dynamic computing environment is still a challenge. By analyzing the pipelining feature within a user task and exploiting the parallelism among ubiquitous processors, we propose UMP-PerComp, a ubiquitous multiprocessor-based pipeline processing architecture to support high performance pervasive application development. UMP-PerComp is an integrated comprehensive framework that makes the development of pervasive applications easier. It includes a set of common services such as context management, resource management, service migration, topology management, that help to build applications and directly simplify the task decoupling and service composition. We describe the design and implementation of UMP-PerComp in this paper. Besides, we develop a distributed JPEG encoding application successfully on the UMP-PerComp. Our experience confirms that UMP-PerComp is a flexible, scalable and practicable framework with high performance.

关键词： pipeline processing Pervasive computing Resource management Context-aware services Computer vision Distributed computing Performance analysis Parallel processing Computer architecture Topology

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Meta-pipeline: A New Execution Mechanism for Distributed pipeline processing

Meta-Pipeline: A New Execution Mechanism for Distributed Pip...

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International Symposium on Parallel and Distributed Computing

作者： Shinichi Yamagiwa Leonel Sousa Tomas Brandao INESC-ID/IST Lisboa Portugal IT-Lisbon/ISCTE Lisboa Portugal

ISBN: (纸本)9780769529172;0769529178

The Caravela platform has been proposed by the authors of this paper to perform distributed stream-based computing on general purpose computation. This platform uses a secured execution unit called flow-model that prevents remote users to touch local information in a computer. The flow-model is assigned to local or remote processing units that execute its program. This paper is focused on a new execution mechanism that defines a pipeline composed by flow-models, called meta-pipeline, and is designed as a set of additional functions of the Caravela platform. The pipeline is executed automatically by the meta-pipeline runtime environment. This paper describes the execution mechanism and also presents an application example.

关键词： pipeline processing Distributed computing Grid computing Data security Application software Information security Data structures Runtime environment Supercomputers Internet

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