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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1993年第8期12卷 1132-1146页

作者： SAKALLAH, KA MUDGE, TN BURKS, TM DAVIDSON, ES Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

In this paper we apply a recently formulated general timing model of synchronous operation to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of level-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads to a comprehensive set of timing constraints. pipeline circuits are important because of their frequent use in computer systems. We define their concurrency as a function of the clock schedule and degree of wave pipelining. We then identify a special class of clock schedules, coincident multiphase clocks, which provide a lower bound on the value of the optimum cycle time. We show that the region of feasible solutions for single-phase clocking can be nonconvex or even disjoint, and derive a closed-form expression for the minimum cycle time of a restricted but practical form of single-phase clocking. We compare these forms of clocking on three pipeline examples and highlight some of the issues in pipeline synchronization.

关键词： Clocks pipeline processing Synchronization Circuits Latches Timing Concurrent computing Propagation delay Processor scheduling Space vector pulse width modulation

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COMPUTATION OF PRIME FACTOR DFT AND DHT/DCCT ALGORITHMS USING CYCLIC AND SKEW-CYCLIC BIT-SERIAL SEMISYSTOLIC IC CONVOLVERS

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IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS 1990年第5期137卷 373-389页

作者： GUDVANGEN, S HOLT, AGJ Department of Electrical and Electronic Engineering University of Newcastle upon Tyne Merz Court Newcastle upon Tyne Tyne and Wear NE1 7RU UK

The paper presents the results of a study of the use of cyclic and skew-cyclic convolvers for the evaluation of the subspace discrete Fourier transforms (DFT) and discrete Hartley transform (DHT) modules resulting from a prime factor decomposition of the DFT and the DHT/discrete cas-cas transform (DCCT), respectively. The method of Rader is employed to convert the subspace DFT/DHT modules into cyclic convolutions (CCs). These are further dissected into CCs and skew-cyclic convolutions (SCCs), respectively, of length ½(Ni − 1), where Ni is the DFT/DHT module length in the ith stage. That allows both real and complex DFT modules, as well as DHT modules, to be computed with the same convolver structure, by a simple reconfiguration of a recombination stage. This has important consequences for hardware implementations as only one type of convolver needs to be fabricated. A family of VLSI building block processors (BBPs) with pipelined bit-serial arithmetic is proposed. All inner products are computed in parallel within each BBP, resulting in a throughput rate inversely proportional to ½(Ni + 1). This leads to easy load balancing, which is discussed first in the context of a array machine and then in that of a multiplexed pipelined machine.

关键词： virtual machines prime factor decomposition transforms multiplexed pipelined machine Algorithms simple reconfiguration VLSI cyclic bit-serial semisystolic IC convolvers skew-cyclic bit-serial semisystolic IC convolvers discrete Fourier transforms pipeline processing Convolvers discrete cas-cas transform Very large scale integration array machine Transforms discrete Hartley transform pipelined bit-serial arithmetic Rader method digital arithmetic application specific integrated circuits ASIC throughput rate microprocessor chips recombination stage subspace evaluation VLSI building block processors fast Fourier transforms

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THE GMICRO/100 32-BIT MICROPROCESSOR

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IEEE MICRO 1991年第4期11卷 20-&页

作者： YOSHIDA, T SHIMIZU, T MIZUGAKI, S HINATA, J MITSUBISHI ELECTR CO KITA ITAMI WORKSDEPT MICROCOMPITAMIHYOGO 664JAPAN

The Gmicro/100, a 32-bit VLSI microprocessor based on the TRON specification, features a five-stage pipeline to execute instructions. A prejump mechanism implemented as a hardware solution for the jump problem executes benchmark programs 16.8 percent faster on the average. Optimized microinstructions permit bitmap-manipulation instructions to perform two to five times faster than the software loops.

关键词： Microprocessors Clocks pipeline processing Transfer functions Read only memory CMOS process Prefetching Decoding Counting circuits Adders

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New Generation Deep Learning for Video Object Detection: A Survey

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IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS 2022年第8期33卷 3195-3215页

作者： Jiao, Licheng Zhang, Ruohan Liu, Fang Yang, Shuyuan Hou, Biao Li, Lingling Tang, Xu Xidian Univ Sch Artificial Intelligence Minist Educ Key Lab Intelligent Percept & Image Understanding Xian 710071 Peoples R China

Video object detection, a basic task in the computer vision field, is rapidly evolving and widely used. In recent years, deep learning methods have rapidly become widespread in the field of video object detection, achieving excellent results compared with those of traditional methods. However, the presence of duplicate information and abundant spatiotemporal information in video data poses a serious challenge to video object detection. Therefore, in recent years, many scholars have investigated deep learning detection algorithms in the context of video data and have achieved remarkable results. Considering the wide range of applications, a comprehensive review of the research related to video object detection is both a necessary and challenging task. This survey attempts to link and systematize the latest cutting-edge research on video object detection with the goal of classifying and analyzing video detection algorithms based on specific representative models. The differences and connections between video object detection and similar tasks are systematically demonstrated, and the evaluation metrics and video detection performance of nearly 40 models on two data sets are presented. Finally, the various applications and challenges facing video object detection are discussed.

关键词： Object detection Feature extraction Deep learning Task analysis Detection algorithms Learning systems Convolution Learning neural networks object detection pipeline processing video signal processing

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A Methodology to Teach Advanced A/D Converters, Combining Digital Signal processing and Microelectronics Perspectives

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IEEE TRANSACTIONS ON EDUCATION 2010年第3期53卷 471-483页

作者： Quintans, Camilo Colmenar, Antonio Castro, Manuel Moure, Maria J. Mandado, Enrique Univ Vigo Dept Elect Technol Vigo 36310 Spain Univ Nacl Educ Distancia Elect & Comp Engn Dept Madrid 28040 Spain

ADCs (analog-to-digital converters), especially pipeline and Sigma-Delta (Sigma-Delta) converters, are designed using complex architectures in order to increase their sampling rate and/or resolution. Consequently, the learning of ADC devices also encompasses complex concepts such as multistage synchronization, latency, oversampling, modulation, noise shaping, filtering, or decimation. This paper is focused on a new learning methodology, based on the simulation of the main circuit topologies used in commercial ADCs, in order to understand their working principles more thoroughly. At the same time, the ADC dynamic and static tests are obtained from the simulation results, and their characterization is obtained at an application level. In this way, the methodology combines the microelectronics perspective, at the design level, with the digital signal processing perspective. This methodology saves time in practical classes and encourages self-learning because it does not require special hardware. Moreover, it uses only software tools that are common in electronic engineering, like the OrCAD PSpice simulator, a C compiler, or a hardware description language (HDL) simulator. The methodology has been validated during two consecutive offerings of academic courses in the Telecommunication Engineering curriculum at Vigo University, Vigo, Spain, and the results obtained are discussed.

关键词： Analog-digital (A/D) conversion circuit testing field programmable gate arrays (FPGAs) learning systems pipeline processing Sigma-Delta modulation simulation

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A 10-Bit 300-MS/s pipelined ADC With Digital Calibration and Digital Bias Generation

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2013年第3期48卷 670-683页

作者： Fang, Bing-Nan Wu, Jieh-Tsorng Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan

A 10-bit pipelined ADC was fabricated using a 65 nm CMOS technology. To reduce power consumption, switching opamps are used. These switching opamps are designed to have a short turn-on time. Digital background calibration is employed to correct the A/D conversion error caused by the low dc gain of the opamps. The biasing voltages in each opamp are automatically generated using digital circuits. This bias scheme can maintain the settling behavior of the opamp against process-voltage-temperature variations. At 300 MS/s sampling rate, the ADC consumes 26.6 mW from a 1 V supply. Its measured DNL and INL are +0.52/-0.4 LSB and +0.99/-1.65 LSB respectively. Its measured SNDR and SFDR are 55.4 dB and 67.2 dB respectively. The chip active area is 0.36 mm(2).

关键词： Analog-to-digital conversion analog digital conversion switching circuits calibration digital background calibration pipeline processing digital bias generation

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DESIGN OF A STATIC MIMD DATA-FLOW PROCESSOR USING MICROpipelineS

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1995年第3期3卷 370-378页

作者： CHANG, CM LU, SL Dept. of Electr. & Comput. Eng. Oregon State Univ. Corvallis OR USA

Control-flow machines are sequential in nature, executing instructions in sequence through control of program counters, whereas data-flow machines execute instructions only as input operands are made available, a process directed at the parallelism inherent within programs. At the architecture level, data-flow machines execute instructions asynchronously. In contrast, at the implementation level, the synchronous design framework of computer systems which employs globally clocked timing discipline has reached its design limits owing to problems of clock distribution. Therefore, renewed interest has been expressed in the design of computer systems based upon an asynchronous (or self-rimed) approach free of the discipline imposed by the global clock. Thus, the design of a static MIMD data-flow processor using micropipelines is presented. The implemented processor, or the micro data-flow processor, differs from processors previously reported insofar as the micro data-flow processor is wholly asynchronous at both the architectural and the implementation levels.

关键词： Data Flow Computing Parallel Architectures pipeline processing System Recovery VLSI Microprocessor Chips Static MIMD Data Flow Processor Micropipelines Asynchronous Configuration Clocks Counting Circuits Computer Architecture Parallel processing Hazards Hardware Distributed Computing Timing pipelines Out Of Order

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A HIGH-PERFORMANCE FPGA-BASED FUZZY PROCESSOR ARCHITECTURE FOR MEDICAL DIAGNOSIS

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IEEE MICRO 2008年第5期28卷 38-52页

作者： Chowdhury, Shubhajit Roy Saha, Hiranmay Jadavpur Univ Dept Elect & Telecommun Engn IC Design & Fabricat Ctr Kolkata 700032 India Jadavpur Univ Dept Elect & Telecommun IC Design & Fabricat Ctr Kolkata 700032 India

AN AUTO-DECISION-MAKING SYSTEM FOR MEDICAL DIAGNOSIS COULD HELP MAKE UP FOR THE LACK OF PHYSICIANS IN RURAL AREAS OF MANY THIRD-WORLD COUNTRIES. THIS HIGH-PERFORMANCE, LOW-POWER, pipelineD PARALLEL FUZZY PROCESSOR BASED ON A DEDICATED SINGLE-CHIP ARCHITECTURE PERFORMS HIGH-SPEED FUZZY INFERENCES WITH processing SPEED UP TO 5.0 MFLIPS AT A CLOCK FREQUENCY OF 40 MHz USING 256 RULES HAVING ONE CONSEQUENT EACH, 16 INPUT VARIABLES, AND 16-BIT RESOLUTION. THE PROCESSOR OPERATES IN REAL TIME PRODUCING RESULTS WITHIN AN INTERVAL OF 1.92 mu S. THE PROCESSOR IMPLEMENTED ON BOARD CONSUMES AS LOW AS 70 MILLIWATT POWER. THE PROCESSOR PERFORMS MEDICAL DIAGNOSIS WITH 97.5 PERCENT ACCURACY.

关键词： Fuzzy Logic Parallel Architectures pipeline processing Rule Based Systems

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A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

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ANALOG INTEGRATED CIRCUITS AND SIGNAL processing 2010年第2期62卷 167-177页

作者： Garcia-Gonzalez, Jose-Manuel Greitschus, Norbert Desel, Thomas Micronas GmbH D-79108 Freiburg Germany

This paper presents the design and implementation of a 12-bit Analog-to-Digital Converter (ADC) for multi-standard TV demodulation applications. The ADC was fabricated in a standard digital 90-nm CMOS process and it is built by means of a front-end sample-and-hold and a cascade of 10 pipeline stages with 1.5-bits resolution. Performance of 60-dB signal-to-noise- ratio and 68-dB spurious-free-dynamic-range is obtained without calibration at 100-MS/s with a 1-VP-P input signal swing. The occupied silicon area is 0.5-mm(2);and the power consumption of 94-mW from a 1.2-V supply.

关键词： Analog-digital conversion CMOS analog integrated circuits Data conversion IF sampling pipeline processing

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A CMOS detector readout front-end for X-ray digital radiography systems

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1996年第1期43卷 249-255页

作者： Adachi, S Tokuda, S Ishida, S Central Research Laboratory SHIMADZU Corporation Kyoto Japan

Described is a 32-channel CMOS readout front-end for X-ray pixel detectors. This front-end is intended for use in digital radiography systems that employ photon counting methods. In many photon counting systems, counting losses become problematic at higher counting rates. To minimize counting losses and ensure true counts at high rates, a synchronous charge sampling method with analog pipelining has been developed and integrated in standard 3-mu m CMOS technology. The device operates with a single 5-V power supply and dissipates 4 mW/channel. The equivalent noise charge (ENC) measured was less than 400 electrons at a counting rate of 8.3 Mcps (with no detector capacitance).

关键词： X-ray detection X-ray detectors Radiography CMOS technology Sampling methods pipeline processing Standards development Power supplies Capacitance measurement Current measurement

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