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检索条件"主题词=pipeline processing"

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A Constructive High-Speed Crypto-mining Approach with Dual SHA-256 on an FPGA

A Constructive High-Speed Crypto-mining Approach with Dual S...

引用

International Conference on VLSI Design

作者： Velamala Pavan Kumar Aravindhan Alagarsamy Department of ECE Centre for Multi-Core Architecture Computation (C-MAC) Koneru Lakshmaiah Education Foundation Vaddeswaram AP India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Blockchain-based cryptocurrency has become extremely popular, especially in various mining approaches and scholarly research. Bitcoin is one of the highest-valued cryptocurrencies mined using many hashing algorithms. The speed and effectiveness of the mining system purely lie in the hash rate and mining board. In view of the mining approach, SHA 256 is one of the most popular and fastest hashing algorithms. In this paper, we propose a high-speed crypto-mining approach using dual SHA256 processing, and the results are compared with various semicustom application-specific integrated circuit (ASIC) architectures. The experimental results indicate an improvement in speed and power consumption of the proposed approach by 6.09% over standard SHA-256 with the Virtex-7 FPGA platform. Similarly, the proposed mining approach significantly improves functional efficiency by 13.40% over the existing hashing architecture. In view of the ASIC platform in comparison with existing hashing architecture, the proposed mining approach offers 13.67% and 16.32% improvement in functional efficiency with 180nm and 90nm respectively.

关键词： Hands Power demand Embedded systems Bitcoin Very large scale integration Throughput Field programmable gate arrays Standards pipeline processing

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Design, Analysis and Verification of AMBA AXI4.0

Design, Analysis and Verification of AMBA AXI4.0

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Visual Analytics and Data Visualization (ICVADV), International Conference on

作者： Aashima Lalit Mohan Saini School of VLSI and Embedded System Design National Institute of Technology Kurukshetra Haryana India Department of Electrical Engineering National Institute of Technology Kurukshetra Haryana India

ISBN: (数字)9798331521394

ISBN: (纸本)9798331521400

AMBA AXI was developed by ARM in 2003 upgrading it to AMBA AXI 4.0 in 2014. AMBA AXI4.0 is a fast, efficient, high frequency, high performance, high bandwidth SOC (system-on-chip) protocol that is used for communication between CPU (central processing unit) and FPGA (field programmable gate arrays). It has five communication channels for reading and writing between master and slave. It supports burst transactions and has handshake mechanism, which makes it suitable for high data transfers rate and for pipeline processing of instructions. It finds applications in various ARM (advanced RISC (reduced instruction set computer) machine) based FPGAs like Zynq-7000, Zynq Ultrascale+, Spartan 7, Arria 10 etc. This work implements the AXI4.0 protocol for communication between master and slave for 32 bits of data transfer and verification of using protocol checker.

关键词： Reduced instruction set computing Visual analytics Communication channels Writing Data transfer Main-secondary Central processing Unit System-on-chip Field programmable gate arrays pipeline processing

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Optimized FPGA Architectures for High-Speed NTT Computation

Optimized FPGA Architectures for High-Speed NTT Computation

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Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), International Conference on

作者： Chetan Harsha Lekkala Sitadevi Bharatula B. Naresh Kumar Reddy K Sarangam Department of ECE Amrita School of Engineering Chennai India

ISBN: (数字)9798350356236

ISBN: (纸本)9798350356243

This research paper aims to enhance the performance of Number Theoretic Transform (NTT) operations in cryptographic applications by leveraging the flexibility and parallel processing capabilities of Field Programmable Gate Arrays (FPGAs). NTT, integral to many cryptographic algorithms, often faces real-time performance challenges due to computational demands. By implementing NTT on FPGAs, this approach introduces features such as parallelism, pipelining, and dynamic memory management, significantly improving computational efficiency. The proposed architecture, utilizing 8T SRAM on the AMD Kintex 7 FPGA KC705 Kit, optimizes memory bandwidth and polynomial multiplication, resulting in a robust, high-speed implementation suitable for real-time cryptographic tasks. Simu-lation results demonstrate substantial performance gains, offering a valuable framework for future cryptographic hardware designs.

关键词： Random access memory Transforms Logic gates Hardware Real-time systems Stability analysis Computational efficiency Cryptography Field programmable gate arrays pipeline processing

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24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input

24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Met...

引用

IEEE International Conference on Solid-State Circuits (ISSCC)

作者： Zijian Liu Minglei Zhang Wei Zhang Yan Zhu Rui P. Martins Chi–Hang Chan University of Macau Macau China Instituto Superior Tecnico/University of Lisboa Lisbon Portugal

ISBN: (数字)9798331541019

ISBN: (纸本)9798331541026

Metastable trajectories in comparators pose unpredictable and non-Gaussian error behaviors in the A/D conversion, which cannot be tolerated by applications such as low-bit-error-rate serial link receivers, radar, and instrumentation [1]–[5]. Time-domain (TD) AOCs [6]–[11] have demonstrated a superior speed to their voltage-domain (VD) SAR and pipeline counterparts thanks to the technology scaling. However, the metastability artifact of the TD ADC is often overlooked, which can be severe under a stringent time deadline and is worth great attention. In literature, TD circuits are often leveraged to facilitate the “metastability detector” [1], while the metastability events indeed cannot be detected because the detector itself can experience metastability. They often detect the error within the loop time, which therefore involves limited additional gain and decision time with extra load on the critical path, leading to a potentially diminished return on error probability $(\mathrm{P}_{\mathrm{m}\mathrm{e}\mathrm{t}\mathrm{a}})$ . Prior work [2], [3] decouples such constraints by pipelining the comparator decisions with additional latches, thus allowing extra gain and time on the detection. This proper unresolved-decision (UD) detection demonstrates an outstanding $\mathrm{P}_{\mathrm{m}\mathrm{e}\mathrm{t}\mathrm{a}}$ in a time-interleaved SAR architecture [3]. However, it compromises latency with $\mathrm{P}_{\mathrm{m}\mathrm{e}\mathrm{t}\mathrm{a}}$ , which is feasible in SARs but not in multistep ADCs.

关键词： Latches Instruments Detectors Receivers Trajectory Solid state circuits Radar applications Time-domain analysis Voltage control pipeline processing

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COMPASS: A Compiler Framework for Resource-Constrained Crossbar-Array Based In-Memory Deep Learning Accelerators

COMPASS: A Compiler Framework for Resource-Constrained Cross...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Jihoon Park Jeongin Choe Dohyun Kim Jae-Joon Kim Seoul National University Seoul South Korea

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Recently, crossbar array based in-memory accelerators have been gaining interest due to their high throughput and energy efficiency. While software and compiler support for the in-memory accelerators has also been introduced, they are currently limited to the case where all weights are assumed to be on-chip. This limitation becomes apparent with the significantly increasing network sizes compared to the in-memory footprint. Weight replacement schemes are essential to address this issue. We propose COMPASS, a compiler framework for resource-constrained crossbar-based processing-in-memory (PIM) deep neural network (DNN) accelerators. COMPASS is specially targeted for networks that exceed the capacity of PIM crossbar arrays, necessitating access to external memories. We propose an algorithm to determine the optimal partitioning that divides the layers so that each partition can be accelerated on chip. Our scheme takes into account the data dependence between layers, core utilization, and the number of write instructions to minimize latency, memory accesses, and improve energy efficiency. Simulation results demonstrate that COMPASS can accommodate much more networks using a minimal memory footprint, while improving throughput by 1.78X and providing 1.28X savings in energy-delay product (EDP) over baseline partitioning methods.

关键词： Computational modeling Simulation Artificial neural networks Throughput In-memory computing Energy efficiency Software System-on-chip Compass pipeline processing

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Design and Research of AI Accelerators for Onboard Computing Platforms Targeting YOLOs Network

Design and Research of AI Accelerators for Onboard Computing...

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International Conference on Computer Research and Development (ICCRD)

作者： Yunlong Wang Hui Zhou Xia Liu Bing Li Yifan Ge Beijing Aerospace Automatic Control Institute Beijing Aerospace Automatic Control Institute Beijing China

ISBN: (数字)9798331531881

ISBN: (纸本)9798331531898

Convolutional Neural Networks (CNNs) play a crucial role in computer vision, with wide applications in image recognition, object tracking, and trajectory optimization. Due to constraints in computation, power consumption, and size in aerospace vehicles, deploying CNN algorithms on target platforms presents a significant challenge in aerospace applications. This paper proposes an accelerator design for the YOLOv3-tiny network tailored to aerospace applications. By employing techniques such as loop partitioning, loop unrolling, and weight sharing, the proposed accelerator enhances computational performance and data reuse efficiency. Additionally, by integrating convolution, activation, and pooling operations into a unified module, this approach reduces the need for intermediate buffers, saving memory and improving acceleration performance. Compared to accelerators that require buffering of convolution results, the proposed design demonstrates superior performance. The accelerator is implemented on the ZYNQ7020 FPGA platform, achieving a peak computational performance of 114.53 GOPS.

关键词： Convolution Computational efficiency Partitioning algorithms Timing Convolutional neural networks Field programmable gate arrays Trajectory optimization Research and development pipeline processing Radio spectrum management

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Enhancing Efficiency in Multicore Processor

Enhancing Efficiency in Multicore Processor

引用

Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE), International Conference

作者： M Balachandra Jayanth Naidu P J Rakesh H R Mihir Sangli Jaideep A Hegwad Radha R C Dept. Electronics and Communication B.M.S. College of Engineering Bangalore India

ISBN: (数字)9798331515911

ISBN: (纸本)9798331515928

Traditional multi-core processor designs face challenges related to underutilized resources during program execution, particularly when cores encounter halts, such as when waiting for subroutines or lengthy tasks. This underutilization can result in reduced system efficiency and responsiveness. To address this problem, our concept incorporates dynamic load balancing, multi-threading, and a 5-stage pipelining approach, allowing a second core to work concurrently with the first core during execution halts. This integrated approach optimizes resource utilization, minimizes idle times, and enhances the overall execution time of programs. Mechanisms for task scheduling, synchronization, and communication are essential for effective implementation, ensuring seamless collaboration between cores without conflicts or data inconsistencies.

关键词： Multicore processing Processor scheduling Multithreading High performance computing Computer architecture Load management Synchronization Resource management Faces pipeline processing

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FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications

FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully...

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IEEE Symposium on High-Performance Computer Architecture

作者： Yongmo Park Aporva Amarnath Subhankar Pal Karthik Swaminathan Alper Buyuktosunoglu Hayim Shaul Ehud Aharoni Nir Drucker Wei D. Lu Omri Soceanu Pradip Bose IBM T. J. Watson Research Center NY USA IBM Research Israel University of Michigan MI USA

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Fully homomorphic encryption (FHE) is a powerful cryptographic technique that enables computation on encrypted data without needing to decrypt it. It has broad applications in scenarios where sensitive data needs to be processed in the cloud or in other untrusted environments. FHE applications are both compute- and memory-intensive, owing to expensive operations on large data. While prior works address the challenges of efficient compute using dedicated hardware, expensive memory transfers still remain a major limiting factor. In this work, we propose a hierarchical near-DRAM processing (NDP) solution for FHE applications, called FHENDI, that harnesses the massive DRAM bank bandwidth. We observe various data access patterns in FHE that reveal distinct levels of parallelism: element-wise, limb-wise, coefficient-wise, and ciphertext-wise. FHENDI exploits these levels of parallelism to map FHE operations and data onto different hierarchies of our design, while addressing three major challenges with NDP for FHE: (i) the lack of bank-to-bank communication support, (ii) limited die-to-die bandwidth, and (iii) large memory access latencies. We resolve the first problem through a novel, conflict-free mapping algorithm built atop localized permutation networks that enables efficient element-wise and butterfly operations in FHE. The second problem is addressed by pipelining the execution of parallel bootstrap operations observed in compiled FHE workloads. Finally, we hide the memory access latency behind computation latency by exploiting a dual-banking scheme and subarray-level parallelism (SLP) of the DRAM banks. We evaluate FHENDI using representative workloads in the domains of privacy-preserving machine learning inference on CNNs and Transformers, database range query, and sorting, that are obtained using a compiler framework called HElayers. We compare FHENDI with a server-class CPU and GPU running the state-of-the-art HEaaN library, and an FHE accelerator ASIC, and repo

关键词： Memory management Random access memory Bandwidth Machine learning Transformers Libraries Cryptography Homomorphic encryption Sorting pipeline processing

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16.2 RNGD: A 5nm Tensor-Contraction Processor for Power-Efficient Inference on Large Language Models

16.2 RNGD: A 5nm Tensor-Contraction Processor for Power-Effi...

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IEEE International Conference on Solid-State Circuits (ISSCC)

作者： Sang Min Lee Hanjoon Kim Jeseung Yeon Minho Kim Changjae Park Byeongwook Bae Yojung Cha Wooyoung Choe Jonguk Choi Younggeun Choi Ki Jin Han Seokha Hwang Kiseok Jang Jaewoo Jeon Hyunmin Jeong Yeonsu Jung Hyewon Kim Sewon Kim Suhyung Kim Won Kim Yongseung Kim Youngsik Kim Hyukdong Kwon Jeong Ki Lee Juyun Lee Kyungjae Lee Seokho Lee Minwoo Noh Junyoung Park Jimin Seo June Paik FuriosaAI Seoul Korea Dongguk University Seoul Korea

ISBN: (数字)9798331541019

ISBN: (纸本)9798331541026

There is a need for an AI accelerator optimized for large language models (LLMs) that combines high memory bandwidth and dense compute power while minimizing power consumption. Traditional architectures [1]–[4] typically map tensor contractions, which is the core computational task in machine learning models, onto matrix multiplication units. However, this approach often falls short in fully leveraging the parallelism and data locality inherent in tensor contractions. In this work, tensor contraction is used as a primitive instead of matrix multiplication, enabling massive parallelism and time-axis pipelining similar to vector processors. Large coarse-grained PEs can be split into smaller compute units called slices, as illustrated in Fig. 16.2.1. Depending on the setup of the fetch network connecting the slices, these slices can function either as one large processing element or as small and independent compute units. Input data are continuously fetched in a pipelined manner through the fetch network, allowing high throughput and efficient data reuse. Since the operation units compute deterministically as configured, accurate cost models for performance and energy can be developed for optimization. The chip specifications are also shown in Fig. 16.2.1.

关键词： Tensors Power demand Large language models Computational modeling Memory management Throughput Solid state circuits Vector processors Optimization pipeline processing

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Cognitive Radio Receiver Design Employing pipeline Successive Approximation ADC

Cognitive Radio Receiver Design Employing Pipeline Successiv...

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Learning and Technology Conference (L&T)

作者： Muhammad Samee Baig Aziza I. Hussein Electrical and Computer Engineering Department Effat University Saudi Arabia College of Engineering Energy and Technology Research Center Effat University Saudi Arabia

ISBN: (数字)9798331532215

ISBN: (纸本)9798331532222

Smart cities require better cellular communication, incorporating a high data rate that satisfies the Internet, cloud computing, and the Internet of Things (IoT) requirements. A high data rate demands higher bandwidth with low latency. However, the already saturated or underutilized frequency spectrum hinders this realization. 5G and cognitive radio technology can enhance spectrum utilization to meet the high data demands of future cellular communication. Cognitive radio uses spectrum sensing to identify underutilized frequencies without interfering with licensed users, addressing the scarcity of the electromagnetic spectrum. In this paper, a cognitive radio receiver design with a SAR analog-to-digital converter, which is recognized for having a modest resolution for high bandwidth signals, is implemented. Moreover, the pipeline technique in the SAR design is proposed to increase the resolution to be suitable for 5G applications. The high-level model of the system is simulated using MATLAB Simulink software. The quantization error observed in the regular SAR ADC design is compared to that in the proposed pipeline SAR ADC, highlighting the enhanced accuracy and efficiency of the pipeline SAR ADC, which makes it suitable for spectrum sensing in next-generation cognitive radio systems.

关键词： Quantization (signal) 5G mobile communication Software packages Smart cities Receivers Bandwidth Sensors Cognitive radio Signal resolution pipeline processing

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