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A pipelineD-IN-TIME PARALLEL ALGORITHM FOR TRANSIENT STABILITY ANALYSIS

IEEE TRANSACTIONS ON POWER SYSTEMS 1991年第2期6卷 715-722页

作者： LASCALA, M SBRIZZAI, R TORELLI, F UNIV BARI DEPT ELECTI-70124 BARIITALY

A new parallel algorithm for transient stability analysis is presented in this paper. Implicit trapezoidal rule is used to discretize the set of algebraic-differential equations which describes the transient stability problem. In this paper, a parallel-in-time formulation has been adopted. A Newton procedure is used to solve the equations which describe the system at each time step whereas a Gauss-Seidel algorithm relaxes the solution across the time steps. A Gauss-Seidel-like procedure can be usefully exploited in parallel processing mode by pipelining the computation through time steps. The paralleism in space of the problem is also exploited. Furthermore, the parallel-in-time formulation is used to change the time steps between iterations by a nested iteration multigrid technique in order to enhance the covergence of the algorithm. The method has the same reliability and model-handling characteristics of typical Dishonest Newton-like procedures. Test results on realistic power systems are presented to show the capability and usefulness of the suggested technique.

关键词： Parallel algorithms Power system transients Equations Gaussian processes Parallel processing Power system reliability Power system modeling Transient analysis Stability analysis pipeline processing

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REDUCING THE BRANCH PENALTY IN pipelineD PROCESSORS

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COMPUTER 1988年第7期21卷 47-55页

作者： LILJA, DJ UNIV ILLINOIS DEPT ELECT & COMP ENGNURBANAIL 61801

A probabilistic model is developed to quantify the performance effects of the branch penalty in a typical pipeline. The branch penalty is analyzed as a function of the relative number of branch instructions executed and the probability that a branch is taken. The resulting model shows the fraction of maximum performance achievable under the given conditions. Techniques to reduce the branch penalty include static and dynamic branch prediction, the branch target buffer, the delayed branch, branch bypassing and multiple prefetching, branch folding, resolution of branch decision early in the pipeline, using multiple independent instruction streams in a shared pipeline, and the prepare-to-branch instruction

关键词： branch bypassing branch folding branch instructions branch penalty branch target buffer delayed branch multiple independent instruction streams multiple prefetching performance performance evaluation pipeline processing pipelined processors prepare-to-branch instruction probabilistic model shared pipeline

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Throughput/area optimised pipelined architecture for elliptic curve crypto processor

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第5期13卷 361-368页

作者： Imrani, Malik Rashid, Muhammad Jafri, Atif Raza Kashif, Muhammad Bahria Univ Dept Elect Engn Islamabad Pakistan Umm Al Qura Univ Dept Comp Engn Mecca Saudi Arabia Istanbul Sehir Univ Dept Elect & Comp Engn Istanbul Turkey

A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first;by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state-of-the-art. The synthesis results over GF(2(m)) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex-7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.

关键词： pipeline processing field programmable gate arrays public key cryptography digital arithmetic elliptic curve crypto processor elliptic curve cryptography arithmetic unit critical path delay clock cycles point addition point doubling point multiplication computation area overhead throughput/area ratio throughput/area optimised pipelined architecture FPGA frequency 369.0 MHz frequency 357.0 MHz frequency 337.0 MHz word length 163.0 bit word length 233.0 bit word length 283.0 bit

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DYNAMIC INSTRUCTION SCHEDULING AND THE ASTRONAUTICS ZS-1

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COMPUTER 1989年第7期22卷 21-35页

作者： SMITH, JE Astronaut. Corp. of America Madison WI

An overview of and survey solutions to the problem of instruction scheduling for pipelined computers are provided. The author demonstrated that dynamic instruction scheduling can provide performance improvements not possible with static scheduling alone. He describes a high-performance computer, the Astronautics ZS-1, which uses novel methods for implementing dynamic scheduling and which can outperform computers using similar-speed technologies that rely solely on state-of-the-art static scheduling techniques

关键词： Astronautics ZS-1 dynamic instruction scheduling high-performance computer instruction scheduling instruction sets performance improvements pipeline processing pipelined computers scheduling

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A TECHNIQUE FOR THE DESIGN OF SYSTOLIC ARRAYS WITH BIT-LEVEL PIPELINING

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CIRCUITS SYSTEMS AND SIGNAL processing 1987年第2期6卷 139-151页

作者： MADAN, BB PARKER, SR ZUBAIR, M INDIAN INST TECHNOL CTR APPL RES ELECTRNEW DELHI 110016INDIA USN POSTGRAD SCHDEPT ELECT & COMP ENGNMONTEREYCA 93940 STANFORD UNIV ELECT ENGNSTANFORDCA 94305

This paper describes a method for designing systolic structures with bit-level pipelining. The proposed technique starts with the signal flow graph representation of a given algorithm. A new signal flow graph rule, called the gain transfer rule is introduced to achieve bit-level pipelining. Using this approach, systolic arrays with bit-level pipelining are derived for a general recursive digital filter and a convolver. The proposed technique is quite general and has also been applied to obtain systolic structures for other problems such as vector transformation. In comparison with some previously reported designs, the new architectures are characterized by simpler basic processing cells and faster data throughput rate or smaller chip area requirements.

关键词： Systolic algorithms pipeline processing signal flow graphs

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REDUCED INSTRUCTION SET COMPUTER ARCHITECTURE

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PROCEEDINGS OF THE IEEE 1988年第1期76卷 38-55页

作者： STALLINGS, W COMP COMM CONSULTING LONDONENGLAND

A tutorial on the reduced instruction set computer (RISC) approach is presented and the key design issues involved in RISC architecture are highlighted. The results of a number of studies on the instruction execution characteristics of compiled high-level-language programs are examined first. The results of these studies inspired the RISC movement. Approaches to tree key RISC design issues are then summarized: optimized register usage, reduced instruction sets, and pipelining. As examples, an experimental system, the Berkeley RISC and a commercial system, the MIPS R2000, are presented. The advantages and disadvantages of a RISC versus CISC (complex instruction set computer) architecture are also discussed

关键词： Berkeley RISC CISC MIPS R2000 RISC architecture compiled high-level-language programs complex instruction set computer instruction execution characteristics optimized register usage pipeline processing pipelining reduced instruction set computer reduced instruction set computing

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High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver

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IET COMMUNICATIONS 2012年第11期6卷 1416-1424页

作者： Karim, S. M. Chakrabarti, I. Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

Novel high-throughput architecture for a turbo decoder, which has been conceived by combining the advantages of pipelining and parallel processing, is proposed. Increase in throughput has been achieved by pipelining the add compare select offset (ACSO) unit and advancing the normalisation process in the ACSO unit based on global overflow protection logic. The proposed turbo decoder also benefits from incorporating low-complexity contention-free interleaver. The present work has demonstrated that a 32 maximum a posteriori probability (MAP) decoder core achieves a data rate of 1.138 Gbps at a maximum clock frequency of 486 MHz when implemented in a 90 nm process technology. Thus, the proposed turbo decoder meets the throughput requirement of modern wireless communication standards like third-generation partnership project (3GPP) long-term evolution (LTE).

关键词： global overflow protection logic 3GPP LTE Reliability maximum likelihood decoding third-generation partnership project long-term evolution normalisation process Communications computing add compare select offset unit Codes high-throughput turbo decoder parallel processing Codecs, coders and decoders bit rate 1.138 Gbit/s parallel architectures maximum a posteriori probability decoder core pipelined parallel architecture size 90 nm MAP decoder core telecommunication computing ACSO unit modern wireless communication standards telecommunication network reliability low-complexity contention-free interleaver turbo codes Parallel architecture pipeline processing frequency 486 MHz Other topics in statistics

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A Multichannel and Compact Time to Digital Converter for Time of Flight Positron Emission Tomography

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2015年第3期62卷 814-823页

作者： Marino, Nahema Baronti, Federico Fanucci, Luca Saponara, Sergio Roncella, Roberto Bisogni, Maria G. Del Guerra, Alberto Univ Pisa Dipartimento Ingn Informaz I-56127 Pisa Italy INFN Pisa I-56127 Pisa Italy Univ Pisa Dipartimento Ingn Informaz I-56122 Pisa Italy Univ Pisa Dipartimento Fis I-56127 Pisa Italy

This paper presents a novel multichannel time to digital converter (TDC) specifically designed for the digitization of photon time of flight (TOF) and energy in positron emission tomography (PET) scanners. A coarse-fine architecture based on a counter combined with a delay locked loop (DLL) is implemented using a fully synchronous approach exploiting the pipeline principle and dynamic logic. This makes the design particularly compact and suitable for multichannel applications. The converter is also able to reject the events generated by the dark noise of the photodetectors used in the PET modules. This significantly reduces the communication bandwidth required for reading the TDC outputs. The TDC has been designed in a 65 nm CMOS process and features 8 channels that provide the arrival time information of an event with an LSB of 102 ps. The core occupies an active area of 0.3 mm(2) mm and consumes 230 mW.

关键词： Delay locked loop pipeline processing time to digital converter

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FORCE-DIRECTED SCHEDULING FOR THE BEHAVIORAL SYNTHESIS OF ASICS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1989年第6期8卷 661-679页

作者： PAULIN, PG KNIGHT, JP CARLETON UNIV DEPT ELECTROTTAWA K1S 5B6ONTARIOCANADA

A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems. An initial version of the force-directed scheduling algorithm at the heart of this methodology was originally presented by the authors in 1987. The latest implementation of the logarithm introduced here reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include multicycle and chained operations; mutually exclusive operations; scheduling under fixed global timing constraints with minimization of functional unit costs, minimization of register costs, and minimization of global interconnect requirements; scheduling with local time constraints (on operation pairs); scheduling under fixed hardware resource constraints; functional pipelining; and structural pipeline (use of pipeline functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach.< >

关键词： Application specific integrated circuits Job shop scheduling Scheduling algorithm pipeline processing Processor scheduling Hardware Control system synthesis Heart Cost function High level synthesis

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A context quality management infrastructure for complex ubiquitous environment

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COMPUTER SYSTEMS SCIENCE AND ENGINEERING 2009年第3期24卷 197-208页

作者： Tang, Siliang Yang, Jianhua Wu, Zhaohui Zhejiang Univ Coll Comp Sci & Technol Hangzhou 310027 Peoples R China

Quality of Context (QoC) will dramatically effect the decisions of context-aware applications especially when deploying them into the real world. Much research has been presented to model and evaluate context information-inherent aspect of QoC by quantifying QoC-parameters. However, only a few context processing infrastructures support QoC control and management. Moreover, when these quality models are deployed into a complex environment, the performance penalty on QoC evolution, context reasoning and inconsistency checking will render most of the presented infrastructures untenable. Furthermore, in a complex world, different applications of the same scenario usually have different criterions for the same context;and context trustworthiness will alter when the environment shifts. Nevertheless, these influences are not mentioned or not well considered on presented QoC models since it is more relevant to QoC management infrastructure. In this paper, we propose a distributed and loosely coupled infrastructure for context processing and QoC management. In this infrastructure, Context processing is separated into several stages that can be performed in parallel by pipelining on different services. These services are designed to cooperate as a flexible and scalable network of distributed machines. In addition, a novel context quality model based on Web Ontology Language Description Logics (OWL-DL), which supports application and situation related QoC evaluation is suggested. Finally, we measure the performance of our prototype by several simulated experiments, and demonstrate the efficacy of this approach through a storeroom scenario and a case study of a context file system application with the help of a Pioneer III-AT mobile robot and a FUSE-based Context file system.

关键词： pipeline processing Distribute INFRASTRUCTURE Mobile robots Context awareness File systems

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