This paper presents the design, implementation, and verification of fine-grained pipelined Least-Mean-Square (lms) adaptive Finite-Impulse-Response (FIR) filters in Virtex FPGA technology. The paper focuses on the imp...
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ISBN:
(纸本)0819437611
This paper presents the design, implementation, and verification of fine-grained pipelined Least-Mean-Square (lms) adaptive Finite-Impulse-Response (FIR) filters in Virtex FPGA technology. The paper focuses on the impact of introducing pipelining into the lms filter. Whilst pipelining provides a speed increase, the additional effect is to introduce delay into the error feedback loop which degrades performance. This effect is overcome through the use of look-ahead and delayed lms based algorithms. In addition, the paper shows that FPGA technology, such as the Virtex FPGA is an ideal platform for this implementation, as the costs of pipelining are offset by the availability of high levels of flipflops within the FPGA architecture. A pipelined momentum lmsalgorithm is identified, which is considered to offer a better convergence behaviour and tracking capability than the pipelined lms algorithm. Detailed performance results including area and timing figures based on actual FPGA layout are given.
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