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International Conference Microelectronics (ICM 2008)

作者： Athow, Jacques L. Al-Khalili, Asim J. Concordia Univ Dept Elect & Comp Engn Montreal PQ H3G 1M8 Canada

ISBN: (纸本)9781424423699

FPGA placement algorithms have stricter location constraints compared to normal ASIC placers. For large circuits, designers often start by using a best local solution and iterate until a reasonable global solution is attained, with optimization criteria such as minimum delay, area and power. This paper presents a modified greedy algorithm for placing Xilinx FPGA blocks, specifically designed for large multipliers. The solution decreases die utilization by aligning pipeline registers in an optimal way with respect to DSP48 blocks, hence decreasing delay, routing interconnect and consequently total power consumption of the design. placement of long-integer multipliers with the proposed algorithm can result in delay reduction of up to 20%.

关键词： Floorplanning FPGA multiplier placement algorithm DSP48

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An optimal sensor placement algorithm (O-SPA) for improving tracking precision of human activity in real-world healthcare systems

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COMPUTER COMMUNICATIONS 2019年 148卷 9-16页

作者： Alarifi, Abdulaziz AlZubi, Ahmad Ali Al-Maitah, Mohammed Al-Kasasbeh, Basil King Saud Univ Community Coll Comp Sci Dept Riyadh Saudi Arabia Arab Open Univ Fac Comp Studies Jeddah Saudi Arabia

In this article, an Optimal Sensor placement algorithm (O-SPA) is designed for improving the precision of human activity. This placement algorithm is designed based on the fact of improving the Rate of Observation (RO) and sensing in the day-to-day activities of human. SPA for RO and sensing improves the analysis precision by accumulating and classifying useful sensor information. Useful sensor information is achieved by approximating the sensor data mitigating positioning errors. The analysis process differentiates useful and less preference information from the placed sensors to reduce complications in classification. This device positioning algorithm is more specific for the precision of data accumulation and manipulation by reducing sensing errors to improve the efficiency of healthcare systems The efficiency of healthcare systems with optimal sensor deployment is measured in terms of accuracy (98.9%), classification time (0.079s), replications (4.12), recall (96.29%), and error factor (0.000021). The efficiency results are the best compared to Hybrid sensing aided human activity recognition (HHAR), Multi-sensor fusion with ensemble pruning system (MSF-EP) and Activities of daily living Compressive sensing (ADL).

关键词： Feature extraction Information sensing Naive Bayes classifier Sensor positioning Wearable sensor placement algorithm

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OPTIMIZATION-BASED placement algorithm FOR BICMOS LEAF CELL GENERATION

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1994年第10期29卷 1227-1237页

作者： XIA, HX LEFEBVRE, MC VINKE, D CARLETON UNIV DEPT ELECTR OTTAWA K1S 5B6 ON CANADA

We present a transistor placement algorithm for the automatic layout synthesis of logic and interface cells comprised of a mixture of MOS and bipolar devices. Our algorithm is applicable to BiCMOS logic cells, ECL logic cells as well as TTL, CMOS and ECL compatible Input/Output (I/O) cells. The transistor placement problem is transformed into a layout floorplan design problem with a mixture of rigid and flexible modules. A constructive ''branch-and-bound'' algorithm is used to minimize the area of synthesized circuits subject to preplacement constraints. Experimental results indicate that the algorithm can produce efficient placements under fixed-height constraints. The design space exploration mechanism can be controlled by the user so as to apportion computing resources judiciously.

关键词： BiCMOS Emitter coupled logic circuits Formal logic Rigid placement algorithm METAL OXIDE SEMICONDUCTORS algorithms layouts mos Oncogenes Transistor Device Component BIPOLAR DEVICES

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A server allocation and placement algorithm for content distribution

A server allocation and placement algorithm for content dist...

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IEEE Information Theory Workshop

作者： Cameron, C Low, SH Wei, DX CALTECH Dept Comp Sci Pasadena CA 91125 USA

ISBN: (纸本)0780376293

It is well known that optimal server placement is NP-hard. We present an approximate model for the case when both clients and servers are dense, and propose a simple server allocation and placement algorithm based on high-rate vector quantization theory. The key idea is to regard the location of a request as a random variable with probability density that is proportional to the demand at that location, and. the problem of server placement as source coding, i.e., to optimally map a source value (request location) to a codeword (server location) to minimize distortion (network cost). This view has led to a joint server allocation and placement algorithm that has a time-complexity that is linear in the number of clients. Simulations are presented to,illustrate its performance.

关键词： client-server systems vector quantisation source coding computational complexity content distribution network server allocation algorithm server placement algorithm high-rate vector quantization theory random variable probability density so placement algorithm Vector quantization source coding Content distribution Random variable client-server systems Servers complexity classes

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The Architecture and placement algorithm for A Uni-Directional Routing Based 3D FPGA

The Architecture and Placement Algorithm for A Uni-Direction...

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12th International Conference on Field-Programmable Technology (FPT)

作者： Hou, Junsong Yu, Heng Ha, Yajun Liu, Xin Natl Univ Singapore Dept Elect & Comp Engn Singapore 117548 Singapore ASTAR Inst Microelectron Singapore Singapore

ISBN: (纸本)9781479921980;9781479921997

Three-Dimensional (3D) FPGA as a promising design trend, achieves significant performance improvement over conventional 2D-based FPGA. The maturity of the uni-directional routing architecture design, which achieves 25% area saving in area-delay-product (ADP) over bi-directional routing architectures, has driven major vendors such as Xilinx and Altera to switch to such architecture in their 2D-based products. However, few studies were contributed to exploring performance-optimal uni-directional 3D routing architectures. In this paper, we propose and evaluate a novel uni-directional 3D routing architecture named UNI-3D. Additionally, in the EDA counterpart, we also propose an improved simulated annealing (SA)-based placement algorithm that caters the unidirectional architecture, to alleviate signal propagation imbalance in the vertical channels resulted from using conventional bi-directional based SA approach. Our simulation results show that our proposed architecture is able to achieve up to 28.44% of delay reduction and 26.21% planar channel width reduction compared with the baseline 2D uni-directional architecture. At the same time, the proposed SA algorithm is able to improve the average vertical channel width up to 16% compared to state-of-the-art works.

关键词： placement algorithm ARCHITECTURE Building construction Network routing channel width performance boost Field programmable gate arrays Building design

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A Parallel GPU Implementation of the TimberWolf placement algorithm 12

A Parallel GPU Implementation of the <i>TimberWolf</i> Place...

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12th International Conference on Information Technology: New Generations ITNG

作者： Al-Kawam, Ahmad Harmanani, Haidar M. Lebanese Amer Univ Dept Math & Comp Sci Byblos 14012010 Lebanon

ISBN: (纸本)9781479988280

GPUs have been gaining acceptance in the electronic design automation field as attractive platforms for implementing and accelerating computationally extensive applications. Researchers agree that it is critical that EDA algorithms exploit future platforms and explore the use of parallel algorithms as we move to the manycore era. This paper describes the implementation of the TimberWolf placement algorithm using CUDA and demonstrates the applicability of GPUs in accelerating electronic design automation tools. The algorithm has been implemented on a Xeon Workstation using C, and achieved a substantial acceleration on an Nvidia Tesla C2070 card.

关键词： CUDA VLSI Design Automation VLSI placement electronic design automation placement algorithm wolf acceleration Computer-Aided Design Parallel algorithms Lumber and lumbering GRAPPER PICK UP Graphics Processing Unit Platform ACCEPTANCE

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Optimized Charge Scheduling of Plug-In Electric Vehicles using Modified placement algorithm 9

Optimized Charge Scheduling of Plug-In Electric Vehicles usi...

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International Conference on Computer Communication and Informatics (ICCCI)

作者： Mohammed, Sheik S. Ahamed, Imthias T. P. Devaraj, D. TKM Coll Engn Dept Elect & Elect Engn Kollam India Kalasalingam Acad Res & Educ Sch Elect Technol Srivilliputhur India

ISBN: (纸本)9781538682593

Electric Vehicles (EV) are found to be promising alternatives for IC engine vehicles as it significantly reduces the fossil fuel usage and in turn, the environmental issues such as CO2 emission, global warming caused by burning the fuel. Energy Storage System (ESS) is the heart of the EV and the batteries need to be charged in a regular interval or upon requirement for the operation of vehicle. EVs are connected to the charging station for charging and the charging is generally scheduled based on the given conditions for optimized charging. The scheduling algorithm creates a charging profile for the EVs to charge the batteries in such a way to meet the objectives of scheduling. This paper presents the electric vehicle charge scheduling using Modified placement algorithm. The objective of the proposed algorithm is to minimize the cost of charging. The algorithm is developed in MATLAB. Electric Vehicles with different power rating and rate of charging are selected to study the performance and accuracy of scheduling algorithm. The charge scheduling of selected vehicles are analyzed based on Time of Use Pricing (ToUP) tariff scheme.

关键词： Electric Vehicle (EV) placement algorithm charge scheduling Time of Use Pricing (ToUP) MATLAB

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Fast placement algorithm for Rectilinear Jigsaw Puzzles

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JOURNAL OF ADVANCED COMPUTATIONAL INTELLIGENCE AND INTELLIGENT INFORMATICS 2006年第3期10卷 323-331页

作者： Murai, Yasuyuki Tsuji, Hiroyuki Tatsumi, Hisayuki Tokumasu, Shinji Kanagawa Inst Technol Dept Informat & Comp Sci 1030 Shimo Ogino Atsugi Kanagawa 2430292 Japan Tsukuba Univ Technol Dept Comp Sci Tsukuba Ibaraki 3050821 Japan

In previous papers, rectilinear jigsaw puzzles have been described as a specialized placement problem such that this has at least one solution to placement, but generally not that many. Instead of adopting the well-known iterative method to solve this problem, a new game-theoretic algorithm is developed by translating the problem to one of checkmate in games analogous to chess or shogi. By extending the game-theoretic algorithm, a much faster algorithm for large puzzles is developed by introducing various heuristics on the placement of pieces. We also proved through numerical experiments that this worked efficiently.

关键词： game theory polyominoes placement algorithm rectilinear jigsaw puzzle

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A New Timing Driven placement algorithm for Dependable Circuits on SRAM-based FPGAs

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2010年第1期4卷 7-7页

作者： Sterpone, Luca Politecn Torino Turin Italy

Electronic systems for safety critical applications such as space and avionics need the maximum level of dependability for guarantee the success of their missions. Simultaneously the computation capabilities required in these fields are constantly increasing for afford the implementation of different kind of applications ranging from signal processing to networking. SRAM-based FPGAs are the candidate devices to achieve this goal thanks to their high versatility of implementing complex circuits with a very short development time. However, in critical environments, the presence of Single Event Upsets (SEUs) affecting the FPGA's functionalities, requires the adoption of specific fault tolerant techniques, like Triple Modular Redundancy (TMR), able to increase the protection capability against radiation effects, but on the other side, introducing a dramatic penalty in terms of performances. In this paper, it is proposed a new timing-driven placement algorithm for implementing soft-errors resilient circuits on SRAM-based FPGAs with a negligible degradation of performance. The algorithm is based on a placement heuristic able to remove the crossing error domains while decreasing the routing congestions and delay inserted by the TMR routing and voting scheme. Experimental analysis performed by timing analysis and SEU static analysis point out a performance improvement of 29% on the average with respect to standard TMR approach and an increased robustness against SEU affecting the FPGA's configuration memory. Accurate analyses of SEUs sensitivity and performance optimization have been performed on a real microprocessor core demonstrating an improvement of performances of more than 62%.

关键词： algorithms Design Performance FPGA fault tolerance placement algorithm

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Research on relay node placement algorithm based on its capacity limitation in WSN

Research on relay node placement algorithm based on its capa...

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International Conference on Security, Pattern Analysis, and Cybernetics (SPAC)

作者： Shouqiang Wang Zengxiao Chi Shen Zhang School of Information Science and Electrical Engineering Shandong Jiaotong University Jinan China

ISBN: (纸本)9781728105529

Energy consumption problem is one of the key issues in Wireless Sensor Network (WSN). Usually sensor nodes are far from one or more sink nodes. In such a case, it calls for deploying some relay nodes as the interval nodes to transmit data from sensor nodes to sink nodes. A relay node placement algorithm in two-tiered WSN model is proposed in this thesis. This algorithm first constructs an optimum spanning tree for unlimited number of relay nodes. Then, a greedy strategy was put forward to remove some relay nodes from the tree. Under the restriction that each relay node must satisfy its communication capacity limitation, the greedy strategy aims to minimize the total energy consumption to prolong the lifetime of whole network.

关键词： Wireless sensor network Sensor node Relay node Energy consumption Trunk Node Wireless sensor networks energy consumption WSN gene Ganglia placement algorithm

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