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Corner block list representation and its application to floorplan optimization

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2004年第5期51卷 228-233页

作者： Hong, XL Dong, SQ Huang, G Cai, YC Cheng, CK Gu, J Tsinghua Univ Comp & Sci Dept Beijing 100084 Peoples R China Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92110 USA Hong Kong Univ Sci & Technol Dept Comp Sci Hong Kong Hong Kong Peoples R China

We propose to use a corner block list (CBL) representation for mosaic floorplans. In a mosaic floorplan, each room has only one block assigned to it. Thus, there is a unique corner room on the to p right corner of the chip. Corner block deletion and corner block insertion keep the floorplan mosaic. Through a recursive deletion process, a mosaic floorplan can be converted to a representation that is named as CBL. Given a CBL, it takes only linear time to construct the floorplan. The CBL is used for the application to very large-scale integration floorplan and building block placement. We adopt a simulated annealing process for the optimization. Soft blocks and the aspect ratio of the chip are taken into account in the optimization process. The experimental results demonstrate that the algorithm is quite promising.

关键词： building block layout floorplanning representation NP hard placement algorithm simulated annealing

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GM-LEARN - AN ITERATIVE LEARNING algorithm FOR CMOS GATE MATRIX LAYOUT

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1990年第4期137卷 301-309页

作者： CHEN, SJ HU, YH UNIV WISCONSIN DEPT ELECT & COMP ENGN MADISON WI 53706 USA

In the paper, an iterative CMOS gate matrix layout algorithm utilising artificial intelligence (A.I.) learning techniques is proposed. This algorithm, called GM-Learn, features a rudimentary learning mechanism which enables iterative improvements of the quality of a gate matrix layout. This is accomplished through the repetitive applications of a one-pass gate matrix layout algorithm, called GM-Plan, to realise a given circuit specification. The function of GM-Learn, is then to ‘learn’ to modify the heuristics used in GM-Plan based on the previous trials. Two AI learning paradigms, known as rote learning and learning by parameter adjustment, are employed. These learning techniques enable GM-Learn to modify its heuristic search parameters based on information obtained from previous iterations. Benchmark test results indicate that this novel algorithm is able to produce a high quality gate matrix layout in only a few iterations. The significance of this new method is that it may be applicable to other combinatorial VLSI physical design problems where heuristic guided search is required.

关键词： Quality Improvement heuristic search Iterative layouts placement algorithm gates Heuristics Rote Learning parameter adjustment PPP1R3A gene Learning methods learning algorithms Artificial Intelligence

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Multi-Objective MDP-Based Routing in UAV Networks for Search-Based Operations

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2024年第9期73卷 13777-13789页

作者： Mahajan, Prateek Palanisamy, Balamurugan Kumar, Anusha Chalapathi, G. S. S. Chamola, Vinay Khabbaz, Maurice Birla Inst Technol & Sci BITS Pilani Dept Elect & Elect Engn EEE Pilani 333031 India Amer Univ Beirut Comp Sci Dept 11-0236-CMPS Beirut Lebanon

Unmanned aerial vehicle (UAV) systems have gained widespread recognition due to their versatility and autonomy. Their deployment for disaster mitigation and management operations is seen as one of their most important applications over the past decade. In such UAV networks, routing plays a crucial role in determining network performance parameters such as network lifetime, data transmission latency, and packet delivery ratio. This paper presents a novel routing mechanism - Multi-Objective Markov Decision Based Routing (MOBMDP) for UAV networks carrying out search-based operations. MOBMDP models routing decisions in a Markov Decision Process (MDP) framework and uses Q-learning to take decisions. It compares routing paths using three metrics, viz., Remaining Energy of the Minimum Energy Node (REMEN), Power Distance ratio (PD), and Expected Delay (ED). Amongst these metrics, PD is a novel metric proposed by this work. PD simultaneously optimizes the energy efficiency and energy distribution in the network. Further, MOBMDP uses a novel reinforcement learning inspired method to estimate transmission delay in a given path. Intensive simulation studies compare MOBMDP to four state-of-the-art routing protocols. Results show a significant improvement in network lifetime, packet delivery ratio, energy efficiency, average data transmission delay, and error in delay estimation.

关键词： Routing Delays Autonomous aerial vehicles Prediction algorithms Q-learning Routing protocols Measurement UAV search and rescue placement algorithm routing protocol network lifetime network coverage transmission delay estimation energy efficiency

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EEVMC: An Energy Efficient Virtual Machine Consolidation Approach for Cloud Data Centers

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IEEE ACCESS 2024年 12卷 105234-105245页

作者： Rehman, Attique Ur Lu, Songfeng Ali, Mubashir Smarandache, Florentin Alshamrani, Sultan S. Alshehri, Abdullah Arslan, Farrukh Huazhong Univ Sci & Technol Sch Cyber Sci & Engn Wuhan 430074 Peoples R China Shenzhen Huazhong Univ Sci & Technol Res Inst Shenzhen 518057 Peoples R China Lahore Garrison Univ Dept Software Engn Lahore 54810 Pakistan Univ New Mexico Math Phys & Nat Sci Div Gallup NM 87301 USA Taif Univ Coll Comp & Informat Technol Dept Informat Technol Taif 21944 Saudi Arabia Al Baha Univ Fac Comp & Informat Technol Informat Technol Dept Al Baha 65799 Saudi Arabia Univ Engn & Technol Dept Elect Engn Lahore 54500 Pakistan

The dynamic landscape of cloud computing design presents significant challenges regarding power consumption and quality of service (QoS). Virtual machine (VM) consolidation is essential for reducing power usage and enhancing QoS by relocating VMs between hosts. OpenStack Neat, a leading framework for VM consolidation, employs the Modified Best-Fit Decreasing (MBFD) VM placement technique, which faces issues related to energy consumption and QoS. To address these issues, we propose an Energy Efficient VM Consolidation (EEVMC) approach. Our method introduces a novel host selection criterion based on the incurred loss during VM placement to identify the most efficient host. For validation, we conducted simulations using real-time workload traces from Planet-Lab and Materna over ten days, leveraging the latest CloudSim toolkit to compare our approach with state-of-the-art techniques. For Planet-Lab's workload, our EEVMC approach shows a reduction in energy consumption by 80.35%, 59.76%, 21.59%, and 7.40%, and fewer system-level agreement (SLA) violations by 94.51%, 94.85%, 47.17%, and 17.78% when compared to Modified Best-Fit Decreasing (MBFD), Power-Aware Best Fit Decreasing (PABFD), Medium Fit Power Efficient Decreasing (MFPED), and Power-Efficient Best-Fit Decreasing (PEBFD), respectively. Similarly, for Materna, EEVMC achieves a reduction in energy consumption by 16.10%, 61.0%, 4.94%, and 4.82%, and fewer SLA violations by 76.99%, 88.88%, 12.50%, and 48.65% against the same benchmarks. Additionally, Loss-Aware Performance Efficient Decreasing (LAPED) significantly reduces the total number of VM migrations and SLA time per active host, indicating a substantial improvement in cloud computing efficiency.

关键词： Cloud computing Data centers Energy efficiency Quality of service Energy consumption Virtual machines Power demand Virtual machine consolidation quality of service energy efficient VM migration placement algorithm OpenStack cloud

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Wire-Length and Run-Time Optimization in FPGA placement Using Hybrid Iterative algorithms

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2021年第5期30卷

作者： Sudhanya, P. Rani, S. P. Joy Vasantha Madras Inst Technol Dept Elect Engn Chennai 600044 Tamil Nadu India

This paper introduces hybrid iterative algorithms that combine Particle Swarm Optimization (PSO) and Simulated Annealing (SA) algorithms for Field Programmable Gate Array (FPGA) placement by considering adaptive inertia weight and local minima avoidance. The algorithms target to optimize the wire-length of the nets, run time and critical path delay in the placement of logic blocks. Using the adaptive inertia weight parameter and local minima avoidance, the hybrid PSO-SA algorithm is modified to Time-varying PSO-SA (TPSO-SA) and Modified PSO-SA (MPSO-SA) algorithm, respectively. These different hybrid PSO-SA algorithms are checked for efficiency by comparing with the Versatile Place and Route (VPR) algorithm of the Verilog to Routing (VTR) tool using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The hybrid PSO-SA algorithms give 537% better results for wire-length cost and 2058% reduction in runtime compared to the VPR placement algorithm on different benchmark circuits. Critical path delay is also taken into consideration.

关键词： FPGA placement algorithm PSO SA PSO-SA BB cost wire-length critical path delay

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Optimization of Layout Solutions of Technological Complexes of Mechanical Assembly Production by Reducing Traffic Flows

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JOURNAL OF MACHINERY MANUFACTURE AND RELIABILITY 2023年第8期52卷 916-929页

作者： Kovalev, A. A. Kravchenko, I. N. Shaposhnikov, Ya. O. Barmina, O. V. Apatenko, A. S. Anoprienko, A. K. Bauman Moscow State Tech Univ Moscow Russia Russian Acad Sci IMASH RAN Mech Engn Res Inst Moscow Russia Russian State Agrarian Univ Moscow Timiryazev Agr Acad Moscow Russia

Methods that make it possible to choose optimal layout solutions for technological complexes are considered. As a result of the analysis, we have established a method for compiling layout diagrams for technological complexes of mechanical assembly production based on minimization of the total annual traffic flow. A block diagram of this department placement algorithm is given based on the chosen method. The proposed method has been implemented based on the example of choice of the optimal layout diagram of the technological complex of mechanical assembly production using the developed program.

关键词： CORELAP layout diagram minimization of total traffic flow solving layout problems placement algorithm closeness ratings

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Efficient On-Chip Task Scheduler and Allocator for Reconfigurable Operating Systems

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IEEE EMBEDDED SYSTEMS LETTERS 2011年第3期3卷 85-88页

作者： Hong, Chuan Benkrid, Khaled Iturbe, Xabier Ebrahim, Ali Arslan, Tughrul Univ Edinburgh Sch Engn Syst Level Integrat Grp Edinburgh EH9 3JL Midlothian Scotland

This letter presents efficient and modular task scheduler and allocator support for dynamically and partially reconfigurable electronic systems. This enables hardware tasks to be preempted and arbitrarily placed at an optimal position on the chip on-the-fly. In particular, we present a novel fault-tolerant allocating algorithm called "best-fit empty area compact (BF-EAC)," and its on-chip implementation on a Xilinx Virtex-4 field-programmable gate array (FPGA), which circumvents emerging faults while maintaining more compact empty areas for emerging tasks. We also present an implementation of the early deadline first (EDF) scheduling heuristic used to optimize the chronological order of execution of hardware tasks to meet real time constraints. Put together, the placement and scheduling architecture efficiently exploits chip resources with a s-grade computing speed and a lightweight footprint (less than 500 slices).

关键词： Allocator dynamic reconfiguration field-programmable gate array (FPGA) partial reconfiguration placement algorithm scheduler

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Phase-Aware Predictive Thermal Modeling for Proactive Load-Balancing of Compute Clusters

Phase-Aware Predictive Thermal Modeling for Proactive Load-B...

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International Conference on Energy Aware Computing

作者： Khanna, Rahul John, Jaiber Rangarajan, Thanunathan Intel Corp Hillsboro OR 97124 USA

ISBN: (纸本)9781467353267;9781467353274

The increasing trend of high density computing environments have exacerbated the cooling infrastructure of the modern datacenters which contributes to mounting energy costs due to uncoordinated operation. By integrating information technology and infrastructure management through continuous monitoring, a balance between energy requirements of compute and cooling equipment can be achieved. Building an online thermal profile calculation with certain measure of accuracy is a complex problem due to the number of variables involved. In this paper we propose a phase-aware workload placement scheme that helps in reducing thermal variance in a cluster of compute nodes. We use a phase-aware machine learning approach to forecast server thermal profile which is then used for predicting the cluster-level thermal variance. We leverage Intel Xeon class server platform sensors and machine monitoring capability for fine grained assessment of power, thermal and compute utilization. We are able achieve thermal balance by applying intelligent placement algorithms by predetermining the thermal impact of a variation in workload's utilization on a prospective cluster of server using the forecasted temperature. Results from a prototype implementation on a typical server-cluster environment have demonstrated accurate thermal prediction and significant reduction in thermal variance.

关键词： Thermal information technology Servers COOLING EQUIPMENT thermal equilibrium Load balancing accuracy of measurement placement algorithm Energy requirements Workload

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Interference Management for Distributed Parallel Applications in Consolidated Clusters 16

Interference Management for Distributed Parallel Application...

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21st International Conference on Architectural Support for Programming Languages and Operating Systems

作者： Han, Jaeung Jeon, Seungheun Choi, Young-ri Huh, Jaehyuk Korea Adv Inst Sci & Technol Sch Comp Daejeon South Korea UNIST Sch Elect & Comp Engn Ulsan South Korea

ISBN: (纸本)9781450340915

Consolidating multiple applications on a system can improve the overall resource utilization of data center systems. However, such consolidation can adversely affect the performance of some applications due to interference caused by resource contention. Despite many prior studies on the interference effects in single-node systems, the interference behaviors of distributed parallel applications have not been investigated thoroughly. With distributed applications, a local interference in a node can affect the whole execution of an application spanning many nodes. This paper studies an interference modeling methodology for distributed applications to predict their performance under interference effects in consolidated clusters. This study first characterizes the effects of interference for various distributed applications over different interference settings, and analyzes how diverse interference intensities on multiple nodes affect the overall performance. Based on the characterization, this study proposes a static profiling-based model for interference propagation and heterogeneity behaviors. In addition, this paper presents use case studies of the modeling method, two interference-aware placement techniques for consolidated virtual clusters, which attempt to maximize the overall throughput or to guarantee the quality-of-service.

关键词： Resource contention consolidated system cloud computing distributed parallel application interference model placement algorithm

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Visualising Software as a Particle System 3

Visualising Software as a Particle System

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3rd IEEE Working Conference on Software Visualization (VISSOFT)

作者： Scarle, Simon Walkinshaw, Neil Univ W England Comp Sci & Creat Technol Bristol BS16 1QY Avon England Univ Leicester Dept Comp Sci Leicester LE1 7RH Leics England

ISBN: (纸本)9781467375269

Current metrics-based approaches to visualise unfamiliar software systems face two key limitations: (1) They are limited in terms of the number of dimensions that can be projected, and (2) they use fixed layout algorithms where the resulting positions of entities can be vulnerable to misinterpretation. In this paper we show how computer games technology can be used to address these problems. We present the PhysVis software exploration system, where software metrics can be variably mapped to parameters of a physical model and displayed via a particle system. Entities can be imbued with attributes such as mass, gravity, and (for relationships) strength or springiness, alongside traditional attributes such as position, colour and size. The resulting visualisation is a dynamic scene;the relative positions of entities are not determined by a fixed layout algorithm, but by intuitive physical notions such as gravity, mass, and drag. The implementation is openly available, and we evaluate it on a selection of visualisation tasks for two openly-available software systems.

关键词： computer games program visualisation software metrics PhysVis software exploration system computer games technology fixed layout algorithm metrics-based approach particle system software visualization Games Layout Measurement Pipelines Software systems Visualization Software measurement Software systems Computer Games Visualization layouts pipeline placement algorithm Video Games automatic game computer software piping

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