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4th Asia Symposium on Quality Electronic Design (ASQED)

作者： Chee, Thomas Goh Fong Seang, Jonathan Ong Yoong Lee, Chun Keong Spansion Penang Sdn Bhd FIZ Bayan Lepas 11900 Penang Malaysia

ISBN: (纸本)9781467326865

Conventional manual placement for decoupling capacitance (decap) is very time consuming and may lead to unavoidable human errors. In VLSI design environments there is a critical need to have an automated way via CAD tools, particularly to ensure quick turn-around times in the face of strong time-to-market pressures. Unfortunately, existing placer algorithms work best on rectangle placement regions, but are less efficient when working on polygon placement regions with more than 4 vertices. Therefore, in this paper, we present and propose a decap placer using new placement algorithm named Size and Level oriented algorithm (SL). This decap placer is implemented with routing and area consideration which works efficiently on not only rectangle but polygon placement regions as well. Furthermore, different placement orientations are implemented also in this decap placer for better decaps placement coverage. In this proposed SL decap placer, it first studied the placement region and defined it using the region defining algorithms. This region defining algorithm is important while dealing with polygon placement region. Next, the placer will place the decaps over the defined region effectively. While placing, in order to maximize the decap population, placer will consider and study the area to start placing the capacitor from biggest size until the smallest size. Placer at the same time will take consideration on the routing as well to take care of the connectivity between placed decaps and the metal overlapping to avoid the metal shortage with top routing metal. Finally, we further improved the coverage of decaps placer by implementing different placement orientation. On top of that, results also showed that the different placement orientations will further increase the decaps population coverage to more than 99% for rectangle placement regions and more than 90% for polygon placement regions. With these both nearly similar coverage results, it can be concluded that the imple

关键词： Decoupling capacitor region defining algorithm placement algorithm placement orientation placement region routing consideration

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A JBits-based incremental design environment with non-preemptive refinement for multi-million gate FPGAs

A JBits-based incremental design environment with non-preemp...

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International Conference on Engineering of Reconfigurable Systems and algorithms

作者： Ma, J Athanas, P Univ New Orleans Dept Elect Engn New Orleans LA 70148 USA

ISBN: (纸本)193241505X

This paper presents an FPGA design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as the gate counts increase to multi-millions. Core-bayed incremental placement algorithms, in conjunction with fast interactive routing, are investigated. to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. When combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An integrated FPGA design environment is then developed based on the incremental placer and its background refiner. The results show that the JBits-based incremental design tool is orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing too much quality.

关键词： incremental techniques placement algorithm JBits APIs design tool

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VM³: Virtual Machine Multicast Migration Based on Comprehensive Load Forecasting 5

VM<SUP>3</SUP>: Virtual Machine Multicast Migration Based on...

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5th International Conference on Cloud Computing (CloudComp)

作者： Guo, Feng Zhang, Dong Liu, Zhengwei Qi, Kaiyuan Syst Soft Dept Inspur State Key Lab High End Server & Storage Technol Jinan 250101 Peoples R China

ISBN: (纸本)9783319160504;9783319160498

Although Virtual Machine (VM) is a fundamental technique for Cloud Operation System (Cloud OS), lack of task model and dynamic usability evaluation are great challenges in VM migration. Hence, this paper proposes a VM multicast migration based on comprehensive load forecasting mechanism named VM3. In this paper, we design a VM placement algorithm based on comprehensive load forecasting, which provides an accurate selection of destination host according to the comprehensive network performance including bandwidth, latency, etc., while only the computing node offloading is considered in the tradition algorithms. Furthermore, we propose a multicast migration mechanism to reduce the computation before migration, and support parallel migration. Through implements and experiments it proves that VM3 improves the accuracy and efficiency of VM cluster migration, and it is practical and widely applicable.

关键词： Cloud operation system Virtual machine Multicast placement algorithm Migration mechanism

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Hardware-accelerator aware VNF-chain recovery 16

Hardware-accelerator aware VNF-chain recovery

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16th International Conference on the Design of Reliable Communication Networks (DRCN)

作者： Sharma, Gourav Prateek Tavernier, Wouter Colle, Didier Pickavet, Mario Univ Ghent IMEC IDLab Dept Informat Technol Ghent Belgium

ISBN: (纸本)9781728163000

Hardware-accelerators in Network Function Virtualization (NFV) environments have aided telecommunications companies (telcos) to reduce their expenditures by offloading compute-intensive VNFs to hardware-accelerators. To fully utilize the benefits of hardware-accelerators, VNF-chain recovery models need to be adapted. In this paper, we present an ILP model for optimizing prioritized recovery of VNF-chains in heterogeneous NFV environments following node failures. We also propose an accelerator-aware heuristic for solving prioritized VNF-chain recovery problems of large-size in a reasonable time. Evaluation results show that the performance of heuristic matches with that of ILP in regard to restoration of high and medium priority VNFchains and a small penalty occurs only for low-priority VNF-chains.

关键词： Terms NFV hardware accelerator Recovery SFC FPGA placement algorithm allocation

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A Comparative Study of Set Associative Memory Mapping algorithms and Their Use for Cache and Main Memory

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IEEE Transactions on Software Engineering 1978年第2期SE-4卷 121-130页

作者： Smith, Alan Jay Computer Science Division Department of Electrical Engineering and Computer Sciences Electronics Research Laboratory University of California Berkeley CA 94720 United States

Set associative page mapping algorithms have become widespread for the operation of cache memories for reasons of cost and efficiency. We show how to calculate analytically the effectiveness of standard bit-selection set associative page mapping or random mapping relative to fully associative (unconstrained mapping) paging. For two miss ratio models, Saltzer's linear model and a mixed geometric model, we are able to obtain simple, closed-form expressions for the relative LRU fault rates. We also experiment with two (infeasible to implement) dynamic mapping algorithms, in which pages are assigned to sets either in an LRU or FIFO manner at fault times, and find that they often yield significantly lower miss ratios than static algorithms such as bit selection. Trace driven simulations are used to generate experimental results and to verify the accuracy of our calculations. We suggest that as electronically accessed third-level memories composed of electron-beam tubes, magnetic bubbles, or charge-coupled devices become available, algorithms currently used only for cache paging will be applied to main memory, for the same reasons of efficiency, implementation ease, and cost. © 1978, IEEE. All rights reserved.

关键词： Buffer memory cache memory linear paging model LRU memory mapping memory technology paging placement algorithm virtual memory

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Exploiting A Constellation of Narrowband RF Sensors to Detect and Track Moving Targets

Exploiting A Constellation of Narrowband RF Sensors to Detec...

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44th Asilomar Conference on Signals, Systems and Computers

作者： Kreucher, Chris Stayman, J. Webster Shapo, Ben Stuff, Mark Integr Applicat Inc 900 Victors WaySuite 220 Ann Arbor MI 48108 USA Johns Hopkins Med Inst Baltimore MD 21205 USA Michigan Tech Res Inst Ann Arbor MI 48105 USA

ISBN: (纸本)9781424497218

This paper presents a novel approach to detecting and tracking moving targets using a constellation of narrowband radio frequency (RF) sensors. Our methodology is an innovative combination of nonlinear estimation and information theoretic sensor placement. The nonlinear filtering approach fully exploits bistatic Doppler measurements made by the sensors without thresholding or linear/Gaussian assumptions, thereby improving the detection/false alarm tradeoff and lowering tracking error. The information theoretic sensor placement algorithm, which is based on minimizing the Cramer-Rao bound (CRB) on localization variance, selects sensor positions that lead to the best estimation performance, thereby maximally exploiting the finite sensing resources. We illustrate the efficacy of the algorithm by showing how well we can track a target using sensors placed using the CRB optimal method as compared to sensors placed randomly.

关键词： Sensors CONSTELLATIONS sensor placement complementary return to bias radiofrequency Narrowband Targets nonlinear estimation Track Moving placement algorithm

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Resource Management for Reconfigurable Computing Systems 6

Resource Management for Reconfigurable Computing Systems

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6th International Conference on Electrical and Electronics Engineering (ICEEE)

作者： Azibi, Abdo Ayadi, Ramzi Kaddachi, Med Lassaad Tech & Vocational Training Corp Directorate Gen Curricula Riyadh Saudi Arabia Dept Elect Coll Technol Alkharj Saudi Arabia

ISBN: (纸本)9781728139104

Task placement problem is one of the most significant and time-consuming parts in reconfigurable computing system. Many investigators have explored on the subject, and most of the traditional studies are focused on free space management in the device. The aim of the free space management algorithm is to find all available free spaces to place a new module. Moreover, the algorithms proposed in the literature are heuristic algorithms, and does not offer a good compromise between the placement quality and the execution time. In order to remedy these problems and to obtain satisfactory results, in this paper we propose a module placement algorithm based on mathematical model that aims to minimize the total communication costs between modules. The results show a significant improvement in communication costs compared to other approaches.

关键词： FPGA (Field Programmable Gate Array) hardware task placement algorithm Resource management

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A Machine Learning Based Quality of Service Estimator for Aerial Wireless Networks 15

A Machine Learning Based Quality of Service Estimator for Ae...

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15th International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob)

作者： Almeida, Eduardo Nuno Fernandes, Kelwin Andrade, Francisco Silva, Pedro Campos, Rui Ricardo, Manuel INESC TEC Porto Portugal Univ Porto Fac Engn Porto Portugal NILG AI Porto Portugal

ISBN: (纸本)9781728133164

Unmanned Aerial Vehicles (UAVs) acting as aerial Wi-Fi Access Points or cellular Base Stations are being considered to deploy on-demand network capacity in order to serve traffic demand surges or replace Base Stations. The ability to estimate the Quality of Service (QoS) for a given network setup may help in solving UAV placement problems. This paper proposes a Machine Learning (ML) based QoS estimator, based on convolutional neural networks, which estimates the QoS for a given network by considering the UAV positions, the user positions and their offered traffic. The ML-based QoS estimator represents a novel paradigm for estimating the QoS in aerial wireless networks. It provides fast and accurate estimations with reduced computational complexity. We demonstrate the usefulness and applicability of the proposed QoS estimator using the ideal UAV placement algorithm. Simulation results show the QoS estimator has an average prediction error lower than 5%.

关键词： Aerial wireless networks Machine learning placement algorithm QoS estimator UAV

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Cache Allocation in CDN: An Evolutionary Game Generalized Particle Model

Cache Allocation in CDN: An Evolutionary Game Generalized Pa...

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1st International Conference on Complex Sciences: Theory and Applications (Complex 2009)

作者： Feng, Xiang Lau, Francis C. M. Gao, Daqi East China Univ Sci & Technol Shanghai 200237 Peoples R China Univ Hong Kong Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9783642024689

Content distribution networks (CDNs) increasingly have been used to reduce the response times experienced by Internet users through placing surrogates close to the clients. This paper presents an object replacement approach based on an evolutionary game generalized particle model (G-GPM). We first propose a problem model for CDNs. The CDN model is then fit into a gravitational field. The origin servers and surrogates are regarded as two kinds of particles which are located in two force-fields. The cache allocation problem is thus transformed into the kinematics and dynamics of the particles in the annular and the round force-fields. The G-GPM approach is unique in four aspects: 1) direct viewing of individual and overall optimization;2) parallel computing (lower time complexity);3) multi-objective solution;and 4) being able to deal with some social interactions behaviors.

关键词： Content Delivery Networks (CDN) cache resource allocation evolutionary game generalized particle model (G-GPM) placement algorithm distributed and parallel algorithm

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High-Level Modeling and Synthesis for Embedded FPGAs

High-Level Modeling and Synthesis for Embedded FPGAs

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Chen, Xiaolin Li, Shuai Schleifer, Jochen Coenen, Thomas Chattopadhyay, Anupam Ascheid, Gerd Noll, Tobias G. Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Rhein Westfal TH Aachen Chair Elect Engn & Comp Syst Aachen Germany

ISBN: (纸本)9783981537000

The fast evolving applications in modern digital signal processing have an increasing demand for components which have high computational power and energy efficiency without compromising the flexibility. Embedded FPGA, which is the customized FPGA with heterogeneous fine-grained application specific operations and routing resources, has shown significantly improved efficiency in terms of throughput, power dissipation and chip area for the target application domain. On the other hand, the complexity of such architecture makes it difficult to perform an efficient architecture exploration and application synthesis without tool support. In this work, we propose a framework for the design of embedded FPGA (eFPGA) architectures, which is extended from an existing framework for Coarse-Grained Reconfigurable Architectures (CGRAs). The framework is composed of a high-level modeling formalism for eFPGAs to explore the mapping space, and a retargetable application synthesis flow. To enable fast design space exploration, a force-directed placement algorithm is proposed. Finally, we demonstrate the efficacy of this framework with demanding application kernels.

关键词： Field programmable gate arrays Frameworks synthesis ARCHITECTURE placement algorithm hierarchical models embedding computational power Space Exploration Building construction Energy efficiency Modeling

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