In this paper, a test access mechanism named TESTLINE and its test time and power optimization algorithm for SOC test is presented. TESTLINE just needs 5 pins and can provide high-speed parallel test scheme. TESTLINE ...
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ISBN:
(纸本)0780366778
In this paper, a test access mechanism named TESTLINE and its test time and power optimization algorithm for SOC test is presented. TESTLINE just needs 5 pins and can provide high-speed parallel test scheme. TESTLINE has a scalable mechanism. Its schematic can be easily configured according to test time and test power. ILP (Integer Linear Programming) is used to find the optimal results. TESTLINE also is a hierarchical Structure. It is easy to build a hierarchical test access mechanism.
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