Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign-precomputation-based a...
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Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign-precomputation-based architecture for approximate rotation using the coordinate rotation digital computer (cordic) algorithm. The proposed architecture is independent of Z-datapath, and involves precomputation of the direction of rotation for each micro-rotation angle. The approach involves selecting the optimal micro-rotation angles from a set of elementary angles in run time. Careful selection and elimination of the redundant micro-rotation angles leads to a maximum of three iterations for a majority of the input angles while also simultaneously reaching within 0:45 (of the desired rotation angle). An field programmable gate array (FPGA) implementation of the proposed rotation mode cordic on XC7K70T-3FBG676 Kintex-7 using Xilinx ISE 13.2 achieves roughly 50% reduction in slice-delay product and power-delay product compared to recent designs. An application of approximate rotation to Hough transform-based lane detection is presented. An efficient algorithm for generation of vote addresses in the parameter space is proposed. It is shown that accurate lane detection is possible along with resource savings using the proposed cordic. The proposed architecture reduces the number of additions roughly by a factor of 20 compared with the conventional method of computing a parameter for each feature point.
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