Considering that the binary-feature-based approximate nearest neighbor (ANN) search technique has not been fully exploited to date, a multisegment binary feature-based hierarchical clustering tree model is proposed to...
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Considering that the binary-feature-based approximate nearest neighbor (ANN) search technique has not been fully exploited to date, a multisegment binary feature-based hierarchical clustering tree model is proposed to achieve fast binary feature matching (FM). In addition, the multisegment vocabulary forest, is developed for the ease of hardware-oriented implementation. During the ANN searching process, the corresponding leaf nodes of each segment of the query feature are returned simultaneously to improve processing speed and accuracy. Furthermore, a hierarchical decomposition based on the term frequency-inverse document frequency is used to reduce the run-time search space and total memory footprint for object database storage. Finally, a fine-grained feature-level fully pipelined object recognition accelerator is implemented based on a dedicated design between FM and object scoring. The performance of the proposed object recognition accelerator is evaluated based on TSMC 65 nm CMOS technology. The accelerator achieves 22 M-vec/s and 6.8 x 10(8) vec/J in throughput and energy efficiency for full-HD resolution, respectively;these results represent a 10.6x and 9x improvement, respectively, relative to current state-of-the-art solutions. The average power consumption is 32.6 mW when operating at 200 MHz.
In this paper, a new architecture for the connection between processing elements in a processing array is proposed. Each PE must be connected to all PEs in a window of size n x n around it. The model is simple and ele...
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In this paper, a new architecture for the connection between processing elements in a processing array is proposed. Each PE must be connected to all PEs in a window of size n x n around it. The model is simple and elegant and the introduced reduction in wiring complexity is drastic: it becomes O(n) instead of O( n 2 ) as it would be in the general simple case where all PEs are connected directly to the central PE of the window. On the other hand, the appropriate hardware for the implementation of the proposed technique is very little compared to the whole PE. Further, the utilization factor of the communication channels is evaluated, while a model for the implementation of the PE for a particular algorithm, is proposed, along with the extension of the introduced wiring model in fully interconnected neural networks.
With the availability of the computer for two-dimensional picture processing, digital restoration of deterministically degraded sampled images is a practical reality. This correspondence presents a mathematical formul...
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With the availability of the computer for two-dimensional picture processing, digital restoration of deterministically degraded sampled images is a practical reality. This correspondence presents a mathematical formulation of discrete modulation transfer compensation of sampled imagery. The analysis makes no assumption regarding the band limitedness of the imaging system and accounts explicitly for the effects of spectrum foldover.
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