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PimBeam: Efficient Regular Path Queries Over Graph Database Using processing-in-memory

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2025年第5期36卷 1042-1057页

作者： Kong, Weihan Zheng, Shengan Hua, Yifan Ma, Ruoyan Wen, Yuheng Wang, Guifeng Zhou, Cong Huang, Linpeng Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ AI Inst MoE Key Lab Artificial Intelligence Shanghai 200240 Peoples R China

Regular path queries (RPQs) in graph databases are bottlenecked by the memory wall. Emerging processing-in-memory (PIM) technologies offer a promising solution to dispatch and execute path matching tasks in parallel within PIM modules. We present an efficient PIM-based data management system tailored for RPQs and graph updates. Our solution, called PimBeam, facilitates efficient batch RPQs and graph updates by implementing a PIM-friendly dynamic graph partitioning algorithm. This algorithm effectively addresses graph skewness issues while maintaining graph locality with low overhead for handling RPQs. PimBeam streamlines label filtering queries by adding a filtering module on the PIM side and leveraging the parallelism of PIM. For the graph updates, PimBeam enhances processing efficiency by amortizing the host CPU's update overhead to PIM modules. Evaluation results of PimBeam indicate 3.59x speedup for RPQs and 29.33x speedup for graph update on average over the state-of-the-art traditional graph database.

关键词： Databases Partitioning algorithms Random access memory Bandwidth Central processing Unit Heuristic algorithms Filtering Artificial intelligence Parallel processing Costs Graph partition load balance path matching processing-in-memory regular path query

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Highly Parallel Regular Expression Matching Using a Real processing-in-memory System

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IEEE ACCESS 2025年 13卷 18937-18951页

作者： Joo, Jeonghyeon Kim, Hyojune Han, Hyuck Im, Eul Gyu Kang, Sooyong Hanyang Univ Dept Comp Sci Seoul 04763 South Korea Dongduk Womens Univ Dept Comp Sci Seoul 02748 South Korea

processing-in-memory (PIM) is an emerging computing paradigm exploiting a cutting-edge memory device (PIM device) that integrates hundreds to thousands of processing units with the memory modules. A data-intensive application running in a host system can offload a portion of its tasks to the processing units in the PIM device, not only to exploit their processing capabilities but also to mitigate the contention in host memory accesses. However, such task offloading has the intrinsic overhead of transferring data between host memory and PIM device, which frequently hinders obtaining performance gain by exploiting the device. In this paper, we present a framework for a PIM-enabled regular expression matching that offloads the pattern-matching (scanning) engine to the PIM device, taking care to minimize the overhead. We implement an application based on the framework that runs on an off-the-shelf PIM system that has recently emerged into the market, and investigate the feasibility of processing-in-memory by comparing its performance with its PIM-oblivious implementation. Experimental results on a real system show that our application reduces the overall execution time by up to 96% compared with the multithreaded PIM-oblivious application when the input data size is 1 GB.

关键词： Random access memory Central processing Unit memory modules Data transfer Instruction sets In-memory computing Parallel processing Resource management Process control Performance evaluation processing-in-memory in-memory processing regular expression matching

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RoPIM: A processing-in-memory Architecture for Accelerating Rotary Positional Embedding in Transformer Models

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2025年第1期24卷 41-44页

作者： Jeon, Yunhyeong Jang, Minwoo Lee, Hwanjun Jung, Yeji Jung, Jin Lee, Jonggeon So, Jinin Kim, Daehoon DGIST Daegu 42988 South Korea Samsung Elect Hwaseong 443743 South Korea Yonsei Univ Seoul 03722 South Korea

The emergence of attention-based Transformer models, such as GPT, BERT, and LLaMA, has revolutionized Natural Language processing (NLP) by significantly improving performance across a wide range of applications. A critical factor driving these improvements is the use of positional embeddings, which are crucial for capturing the contextual relationships between tokens in a sequence. However, current positional embedding methods face challenges, particularly in managing performance overhead for long sequences and effectively capturing relationships between adjacent tokens. In response, Rotary Positional Embedding (RoPE) has emerged as a method that effectively embeds positional information with high accuracy and without necessitating model retraining even with long sequences. Despite its effectiveness, RoPE introduces a considerable performance bottleneck during inference. We observe that RoPE accounts for 61% of GPU execution time due to extensive data movement and execution dependencies. In this paper, we introduce RoPIM, a processing-in-memory (PIM) architecture designed to efficiently accelerate RoPE operations in Transformer models. RoPIM achieves this by utilizing a bank-level accelerator that reduces off-chip data movement through in-accelerator support for multiply-addition operations and minimizes operational dependencies via parallel data rearrangement. Additionally, RoPIM proposes an optimized data mapping strategy that leverages both bank-level and row-level mappings to enable parallel execution, eliminate bank-to-bank communication, and reduce DRAM activations. Our experimental results show that RoPIM achieves up to a 307.9x performance improvement and 914.1x energy savings compared to conventional systems.

关键词： Graphics processing units Transformers Random access memory Kernel Computer architecture Natural language processing Computational modeling Vectors Inverters Encoding processing-in-memory transformer model rotary positional embedding

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NPC: A Non-Conflicting processing-in-memory Controller in DDR memory Systems

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IEEE TRANSACTIONS ON COMPUTERS 2025年第3期74卷 1025-1039页

作者： Lee, Seungyong Lee, Sanghyun Seo, Minseok Park, Chunmyung Shin, Woojae Lee, Hyuk-Jae Kim, Hyun Seoul Natl Univ Interuniv Semicond Res Ctr Dept Elect & Comp Engn Seoul 08826 South Korea SK Hynix Inc Icheon 17336 Gyeonggi Do South Korea Seoul Natl Univ Sci & Technol Dept Elect & Informat Engn Seoul 01811 South Korea Seoul Natl Univ Sci & Technol Res Ctr Elect & Informat Technol Seoul 01811 South Korea

processing-in-memory (PIM) has emerged as a promising solution to address the memory wall problem. Existing memory interfaces must support new PIM commands to utilize PIM, making the definition of PIM commands according to memory modes a major issue in the development of practical PIM products. For performance and OS-transparency, the memory controller is responsible for changing the memory mode, which requires modifying the controller and resolving conflicts with existing functionalities. Additionally, it must operate to minimize mode transition overhead, which can cause significant performance degradation. In this study, we present NPC, a memory controller designed for mode transition PIM that delivers PIM commands via the DDR interface. NPC issues PIM commands while transparently changing the memory mode with a dedicated scheduling policy that reduces the number of mode transitions with aggregative issuing. Moreover, existing functions, such as refresh, are optimized for PIM operation. We implement NPC in hardware and develop a PIM emulation system to validate it on FPGA platforms. Experimental results reveal that NPC is compatible with existing interfaces and functionality, and the proposed scheduling policy improves performance by 2.2x with balanced fairness, achieving up to 97% of the ideal performance. These findings have the potential to aid the application of PIM in real systems and contribute to the commercialization of mode transition PIM.

关键词： memory management Processor scheduling Random access memory Error correction codes Computers Calibration Microprocessors Micromechanical devices Hardware Degradation processing-in-memory memory controller DRAM scheduling policy

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processing-in-memory Technology for Machine Learning: From Basic to ASIC

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第6期69卷 2598-2603页

作者： Taylor, Brady Zheng, Qilin Li, Ziru Li, Shiyu Chen, Yiran Duke Univ Dept Elect & Comp Engn Durham NC 27707 USA

Due to the need for computing models that can process large quantities of data efficiently and with high throughput in many state-of-the-art machine learning algorithms, the processing-in-memory (PIM) paradigm is emerging as a potential replacement for standard digital architectures on these workloads. In this tutorial, we review the progress of PIM technology in recent years, at both the circuit and architecture level. We further present an analysis of when and how PIM technology surpasses the performance of conventional architectures. Finally, we outline our vision for the future of PIM technology.

关键词： processing-in-memory machine learning accelerator analogcomputation dataflow optimization

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processing-in-memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency 33

Processing-in-Memory Accelerator for Dynamic Neural Network ...

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33rd IEEE International System on Chip Conference (IEEE SOCC)

作者： Yang, Li He, Zhezhi Angizi, Shaahin Fan, Deliang Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85281 USA

ISBN: (纸本)9781728187464

With the widely deployment of powerful deep neural network (DNN) into smart, but resource limited IoT devices, many prior works have been proposed to compress DNN in a hardware-aware manner to reduce the computing complexity, while maintaining accuracy, such as weight quantization, pruning, convolution decomposition, etc. However, in typical DNN compression methods, a smaller, but fixed, network structure is generated from a relative large background model for resource limited hardware accelerator deployment. However, such optimization lacks the ability to tune its structure on-the-fly to best fit for a dynamic computing hardware resource allocation and workloads. In this paper, we mainly review two of our prior works [1], [2] to address this issue, discussing how to construct a dynamic DNN structure through either uniform or non-uniform channel selection based sub-network sampling. The constructed dynamic DNN could tune its computing path to involve different number of channels, thus providing the ability to trade-off between speed, power and accuracy on-the-fly after model deployment. Correspondingly, an emerging Spin-Orbit Torque Magnetic Random-Access-memory (SOT-MRAM) based processing-in-memory (PIM) accelerator will also be discussed for such dynamic neural network structure.

关键词： processing-in-memory Dynamic neural network

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processing-in-memory Enabled Graphics Processors for 3D Rendering 23

Processing-in-Memory Enabled Graphics Processors for 3D Rend...

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23rd IEEE International Symposium on High Performance Computer Architecture (HPCA)

作者： Xie, Chenhao Song, Shuaiwen Leon Wang, Jing Zhang, Weigong Fu, Xin Univ Houston ECE Dept Houston TX 77004 USA PNNL HPC Grp Richland WA USA Capital Normal Univ Coll Informat Engn Beijing Adv Innovat Ctr Imaging Technol Beijing Peoples R China

ISBN: (纸本)9781509049851

The performance of 3D rendering of Graphics processing Unit that converts 3D vector stream into 2D frame with 3D image effects significantly impacts users gaming experience on modern computer systems. Due to its high texture throughput requirement, main memory bandwidth becomes a critical obstacle for improving the overall rendering performance. 3D-stacked memory systems such as Hybrid memory Cube provide opportunities to significantly overcome the memory wall by directly connecting logic controllers to DRAM dies. Although recent works have shown promising improvement in performance by utilizing HMC to accelerate special-purpose applications, a critical challenge of how to effectively leverage its high internal bandwidth and computing capability in GPU for 3D rendering remains unresolved. Based on the observation that texel fetches greatly impact off-chip memory traffic, we propose two architectural designs to enable processing-in-memory based GPU for efficient 3D rendering. Additionally, we employ camera angles of pixels to control the performance-quality tradeoff of 3D rendering. Extensive evaluation across several real-world games demonstrates that our design can significantly improve the performance of texture filtering and 3D rendering by an average of 3.97X (up to 6.4X) and 43% (up to 65%) respectively, over the baseline GPU. Meanwhile, our design provides considerable memory traffic and energy reduction without sacrificing rendering quality.

关键词： GPU processing-in-memory 3D-Stacked memory Approximate Computing 3D Rendering

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processing-in-memory Designs Based on Emerging Technology for Efficient Machine Learning Acceleration 24

Processing-in-Memory Designs Based on Emerging Technology fo...

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34th Great Lakes Symposium on VLSI (GLSVLSI)

作者： Kim, Bokyung Li, Hai Helen Chen, Yiran Duke Univ Elect & Comp Engn Durham NC 27708 USA

ISBN: (纸本)9798400706059

The unprecedented success of artificial intelligence (AI) enriches machine learning (ML)-based applications. The availability of big data and compute-intensive algorithms empowers versatility and high accuracy in ML approaches. However, the data processing and innumerable computations burden conventional hardware systems with high power consumption and low performance. Breaking away from the traditional hardware design, non-conventional accelerators exploiting emerging technology have gained significant attention with a leap forward since the emerging devices enable processing-in-memory (PIM) designs of dramatic improvement in efficiency. This paper presents a summary of state-of-the-art PIM accelerators over a decade. The PIM accelerators have been implemented for diverse models and advanced algorithm techniques across diverse neural networks in language processing and image recognition to expedite inference and training. We will provide the implemented designs, methodologies, and results, following the development in the past years. The promising direction of the PIM accelerators, vertically stacking for More than Moore, is also discussed.

关键词： processing-in-memory Accelerators Emerging Technology Memristor Deep Learning

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processing-in-memory Architecture with Precision-Scaling for Malware Detection 37

Processing-in-Memory Architecture with Precision-Scaling for...

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37th International Conference on VLSI Design (VLSID) / 23rd International Conference on Embedded Systems (ES)

作者： Kasarapu, Sreenitha Bavikadi, Sathwika Dinakarrao, Sai Manoj Pudukotai George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9798350384406

The wide adaptations of embedded systems in multiple fields have led to smart connectivity across devices and enhanced computation capabilities. Despite the vast applications in different areas, embedded systems face huge security threats. One of the critical security vulnerabilities is caused by malicious software a.k.a malware. Successful malware detection by employing Machine Learning (ML) is widely adopted in many systems. One of the prominent challenges in implementing neural network (NN) architectures is the requirement to have a large number of computational resources. Furthermore, the frequent movement of data between logic and memory units adds large overheads. Conversely, the IoT and edge devices are often limited in terms of the number of available resources. As a panacea, we introduce a PIM-based architecture to address such concerns and improve memory access latency. Such a paradigm further enriches the malware detection latency by mitigating the data transfer latency. To further improve the throughput and energy consumption, we employ precision scaling for the PIM-based malware detection in this work. We observe a malware detection accuracy of 98% with the proposed technique. Our proposed PIM architecture has 1.09x higher throughput than other traditional PIM architectures. Furthermore, precision scaling and PIM improve the energy efficiency by 1.5x compared to the fullprecision operation without any penalty in performance.

关键词： look-up-tables Machine Learning malware detection Precision scaling processing-in-memory security

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processing-in-memory for Databases: Query processing and Data Transfer 19

Processing-in-Memory for Databases: Query Processing and Dat...

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19th International Workshop on Data Management on New Hardware (DaMoN)

作者： Baumstark, Alexander Jibril, Muhammad Attahir Sattler, Kai-Uwe TU Ilmenau Ilmenau Germany

ISBN: (纸本)9798400701917

The processing-in-memory (PIM) paradigm promises to accelerate data processing by pushing down computation to memory, reducing the amount of data transfer between memory and CPU, and - in this way - relieving the CPU from processing. Particularly, in in-memory databases memory access becomes a performance bottleneck. Thus, PIM seems to offer an interesting solution for database processing. In this work, we investigate how commercially available PIM technology can be leveraged to accelerate query processing by offloading (parts of) query operators to memory. Furthermore, we show how to address the problem of limited PIM storage capacity by interleaving transfer and computation and present a cost model for the data placement problem.

关键词： processing-in-memory query processing database accelerator

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