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检索条件"主题词=processing-in-memory"

共 354 条记录，以下是91-100 订阅

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Data-Centric Computing Frontiers: A Survey On processing-in-memory 16

Data-Centric Computing Frontiers: A Survey On Processing-In-...

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International Symposium on memory Systems (MEMSYS)

作者： Siegl, Patrick Buchty, Rainer Berekovic, Mladen Tech Univ Carolo Wilhelmina Braunschweig Abt Tech Informat EIS Muhlenpfordtstr 23 D-38106 Braunschweig Germany

ISBN: (纸本)9781450343053

A major shift from compute-centric to data-centric computing systems can be perceived, as novel big data workloads like cognitive computing and machine learning strongly enforce embarrassingly parallel and highly efficient processor architectures. With Moore's law having surrendered, innovative architectural concepts as well as technologies are urgently required, to enable a path for tackling exascale and beyond - even though current computing systems face the inevitable instruction-level parallelism, power, memory, and bandwidth walls. As part of any computing system, the general perception of memories depicts unreliability, power hungriness and slowness, resulting in a future prospective bottleneck. The latter being an outcome of a pin limitation derived by packaging constraints, an unexploited tremendous row bandwidth is determinable, which off-chip diminishes to a hare minimum. Building upon a shift towards data-centric computing systems, the near-memory processing concept seems to be most promising, since power efficiency and computing performance increase by co-locating tasks on bandwidth rich in-memory processing units, whereas data motion mitigates by the avoidance of entire memory hierarchies. By considering the umbrella of near data. processing as the urgent required breakthrough for future computing systems, this survey presents its derivations with a special emphasis on processing-in-memory (PIM), highlighting historical achievements in technology as well as architecture while depicting its advantages and obstacles.

关键词： memory wall bandwidth wall processing-in-memory near-data processing

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Accelerating Neural Network Training with processing-in-memory GPU 22

Accelerating Neural Network Training with Processing-in-Memo...

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22nd IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGrid)

作者： Fei, Xiang Han, Jianhui Huang, Jianqiang Zheng, Weimin Zhang, Youhui Tsinghua Univ Beijing Natl Res Ctr Informat Sci & Technol Dept Comp Sci & Technol Beijing Peoples R China Tsinghua Univ Sch Integrated Circuits Beijing Peoples R China Qinghai Univ Dept Comp Technol & Applicat Xining Peoples R China

ISBN: (纸本)9781665499569

processing-in-memory (PIM) architecture is promising for accelerating deep neural network (DNN) training due to its low-latency and energy-efficient data movement between computation units and the memory. This paper explores a novel GPU-PIM architecture for DNN training, where streaming multiprocessors of GPU are integrated into the logic layer of 3D memory stack, and multiple such stacks are connected to form a PIM-network. Two corresponding optimization strategies are proposed. The first is to increase the computational parallelism of the data-parallel training mode with the large memory, high bandwidth/high network transmission speed of GPU-PIM. The second is further utilizing the optimized model-parallel training to significantly reduce the communication overhead: We propose a mapping scheme to decide the proper parallelization for different DNN layers on the proposed architecture. Experiments show that the proposed architecture outperforms the baseline GPU by 35.5% and 59.9% and reduces energy consumption by 28.2% and 27.8% for the two benchmarks we evaluated.

关键词： Hybrid memory Cube GPU processing-in-memory deep neural network

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PIM-STM: Software Transactional memory for processing-in-memory Systems 24

PIM-STM: Software Transactional Memory for Processing-In-Mem...

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29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Lopes, Andre Castro, Daniel Romano, Paolo Univ Lisbon INESC ID Lisbon Portugal Univ Lisbon Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9798400703850

processing-in-memory (PIM) is a novel approach that augments existing DRAM memory chips with lightweight logic. By allowing to offload computations to the PIM system, this architecture allows for circumventing the data-bottleneck problem that affects many modern workloads. This work tackles the problem of how to build efficient software implementations of the Transactional memory (TM) abstraction by introducing PIM-STM, a library that provides a range of diverse TM implementations for UPMEM, the first commercial PIM system. Via an extensive study we assess the efficiency of alternative choices in the design space of TM algorithms on this emerging architecture. We further quantify the impact of using different memory tiers of the UPMEM system (having different trade-offs for what concerns latency vs capacity) to store the metadata used by different TM implementations. Finally, we assess the gains achievable in terms of performance and memory efficiency when using PIM-STM to accelerate TM applications originally conceived for conventional CPU-based systems.

关键词： processing-in-memory Transactional memory Concurrent Systems Concurrency control

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An 8-T processing-in-memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips

An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel A...

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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Chen, Leyi He, Junxian Yu, Jianyi Wang, Haibing Lu, Jing Liu, Liyuan Wu, Nanjian Shi, Cong Min, Tian Chongqing Univ Sch Microelect & Commun Engn Chongqing 400044 Peoples R China Chinese Acad Sci Inst Semiconductors Beijing 100083 Peoples R China

ISBN: (纸本)9781665450737

Vision chip is a high-speed image processing device, featuring a massively-parallel pixel-level processing element (PE) array to boost pixel processing speed. However, the collocated processing unit and fine-grained data memory unit inside each PE impose a huge requirement on memory access bandwidth as well as big area and energy consumption. To overcome this bottleneck, this paper proposes a full custom 8T SRAM-based processing-in-memory (PIM) architecture to realize pixel-parallel array processor for high-speed energy-efficient vision chips. The proposed PIM architecture is constructed by emending multiplexer-based computing circuits into a dual port 8T SRAM array, so as to form a PIM PE array. Each PIM PE holds a 66-bit 8T SRAM cell block embedding in-memory logic functions, of which 64-bit 8T SRAM cells serving as the PE memory, 2-bit 8T SRAM cells acting as a buffer register in the PE. A full custom physical layout of a 16 x 16 prototyping PIM PE array is designed and simulated using a 65 nm CMOS technology. The simulation results demonstrate that our proposed PIM PE architecture can achieve 200 MHz operation at 1.2 V, and reach a high energy efficiency of 3.97 TOPS/W while keeping a compact area of 0.129 mm(2).

关键词： vision chip processing-in-memory processing element pixel-parallel

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A Customized processing-in-memory Architecture for Biological Sequence Alignment 29

A Customized Processing-in-Memory Architecture for Biologica...

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29th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Akbari, Nasrin Modarressi, Mehdi Daneshtalab, Masoud Loni, Mohammad Univ Tehran Coll Engn Dept Elect & Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Malardalen Univ MDH Vasteras Sweden Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781538674796

Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. The design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation.

关键词： Sequence Alignment Accelerator processing-in-memory

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PSB-RNN: A processing-in-memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks

PSB-RNN: A Processing-in-Memory Systolic Array Architecture ...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Challapalle, Nagadastagiri Rampalli, Sahithi Chandran, Makesh Kalsi, Gurpreet Subramoney, Sreenivas Sampson, John Narayanan, Vijaykrishnan Penn State Univ University Pk PA 16802 USA Intel Labs Processor Architecture Res Lab Bangalore Karnataka India

ISBN: (纸本)9783981926347

Recurrent Neural Networks (RNNs) are widely used in Natural Language processing (NLP) applications as they inherently capture contextual information across spatial and temporal dimensions. Compared to other classes of neural networks, RNNs have more weight parameters as they primarily consist of fully connected layers. Recently, several techniques such as weight pruning, zero-skipping, and block circulant compression have been introduced to reduce the storage and access requirements of RNN weight parameters. In this work, we present a ReRAM crossbar based processing-in-memory (PIM) architecture with systolic dataflow incorporating block circulant compression for RNNs. The block circulant compression decomposes the operations in a fully connected layer into a series of Fourier transforms and point-wise operations resulting in reduced space and computational complexity. We formulate the Fourier transform and point-wise operations into in-situ multiply-and-accumulate (MAC) operations mapped to ReRAM crossbars for high energy efficiency and throughput. We also incorporate systolic dataflow for communication within the crossbar arrays, in contrast to broadcast and multicast communications, to further improve energy efficiency. The proposed architecture achieves average improvements in compute efficiency of 44x and 17x over a custom FPGA architecture and conventional crossbar based architecture implementations, respectively.

关键词： Recurrent neural network processing-in-memory Block circulant Fourier transform ReRAM Crossbar

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TransPimLib: Efficient Transcendental Functions for processing-in-memory Systems

TransPimLib: Efficient Transcendental Functions for Processi...

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IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

作者： Item, Maurus Gomez-Luna, Juan Guo, Yuxin Oliveira, Geraldo F. Sadrosadati, Mohammad Mutlu, Onur Swiss Fed Inst Technol Zurich Switzerland

ISBN: (纸本)9798350397390

processing-in-memory (PIM) promises to alleviate the data movement bottleneck in modern computing systems. However, current real-world PIM systems have the inherent disadvantage that their hardware is more constrained than in conventional processors (CPU, GPU), due to the difficulty and cost of building processing elements near or inside the memory. As a result, general-purpose PIM architectures support fairly limited instruction sets and struggle to execute complex operations such as transcendental functions and other hard-to-calculate operations (e.g., square root). These operations are particularly important for some modern workloads, e.g., activation functions in machine learning applications. In order to provide support for transcendental (and other hardto-calculate) functions in general-purpose PIM systems, we present TransPimLib, a library that provides CORDIC-based and LUT-based methods for trigonometric functions, hyperbolic functions, exponentiation, logarithm, square root, etc. We develop an implementation of TransPimLib for the UPMEM PIM architecture and perform a thorough evaluation of TransPimLib's methods in terms of performance and accuracy, using microbenchmarks and three full workloads (Blackscholes, Sigmoid, Softmax). We open-source all our code and datasets at https://***/CMU-SAFARI/transpimlib.

关键词： processing-in-memory processing-near-memory transcendental functions activation functions machine learning

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AESPA: Asynchronous Execution Scheme to Exploit Bank-Level Parallelism of processing-in-memory 23

AESPA: Asynchronous Execution Scheme to Exploit Bank-Level P...

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56th IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Kal, Hongju Yoo, Chanyoung Ro, Won Woo Yonsei Univ Seoul South Korea

ISBN: (纸本)9798400703294

This paper presents an asynchronous execution scheme to leverage the bank-level parallelism of near-bank processing-in-memory (PIM). We observe that performing memory operations underutilizes the parallelism of PIM computation because near-bank PIMs are designated to operate all banks synchronously. The all-bank computation can be delayed when one of the banks performs the basic memory commands, such as read/write requests and activation/precharge operations. We aim to mitigate the throughput degradation and especially focus on execution delay caused by activation/precharge operations. For all-bank execution accessing the same row of all banks, a large number of activation/precharge operations inevitably occur. Considering the timing parameter limiting the rate of row-open operations (tFAW), the throughput might decrease even further. To resolve this activation/precharge overhead, we propose AESPA, a new parallel execution scheme that operates banks asynchronously. AESPA is different from the previous synchronous execution in that (1) the compute command of AESPA targets a single bank, and (2) each processing unit computes data stored in multiple DRAM columns. By doing so, while one bank computes multiple DRAM columns, the memory controller issues activation/precharge or PIM compute commands to other banks. Thus, AESPA hides the activation latency of PIM computation and fully utilizes the aggregated bandwidth of the banks. For this, we modify hardware and software to support vector and matrix computation of previous near-bank PIM architectures. In particular, we change the matrix-vector multiplication based on an inner product to fit it on AESPA PIM. Previous matrix-vector multiplication requires data broadcasting and simultaneous computation across all processing units. By changing the matrix-vector multiplication method, AESPA PIM can transfer data to respective processing units and start computation asynchronously. As a result, the near-bank PIMs adopting AESPA a

关键词： processing-in-memory Execution Method Matrix-Vector Multiplication

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Massively Parallel Skyline Computation For processing-in-memory Architectures 18

Massively Parallel Skyline Computation For Processing-In-Mem...

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27th IEEE/ACM/IFIP International Conference on Parallel Architectures and Compilation Techniques (PACT)

作者： Zois, Vasileios Gupta, Divya Tsotras, Vassilis J. Najjar, Walid A. Roy, Jean-Francois Univ Calif Riverside Riverside CA 92521 USA UPMEM SAS Grenoble France

ISBN: (纸本)9781450359863

processing-in-memory (PIM) is an increasingly popular architecture aimed at addressing the 'memory wall' crisis by prioritizing the integration of processors within DRAM. It promotes low data access latency, high bandwidth, massive parallelism, and low power consumption. The skyline operator is a known primitive used to identify those multi-dimensional points offering optimal trade-offs within a given dataset. For large multidimensional dataset, calculating the skyline is extensively compute and data intensive. Although, PIM systems present opportunities to mitigate this cost, their execution model relies on all processors operating in isolation with minimal data exchange. This prohibits direct application of known skyline optimizations which are inherently sequential, creating dependencies and large intermediate results that limit the maximum parallelism, throughput, and require an expensive merging phase. In this work, we address these challenges by introducing the first skyline algorithm for PIM architectures, called DSky. It is designed to be massively parallel and throughput efficient by leveraging a novel work assignment strategy that emphasizes load balancing. Our experiments demonstrate that it outperforms the state-of-the-art algorithms for CPUs and GPUs, in most cases. DSky achieves 2x to 14x higher throughput compared to the state-of-the-art solutions on competing CPU and GPU architectures. Furthermore, we showcase DSky's good scaling properties which are intertwined with PIM's ability to allocate resources with minimal added cost. In addition, we showcase an order of magnitude better energy consumption compared to CPUs and GPUs.

关键词： processing-in-memory skyline queries pareto dominance massive parallelism processing-near-memory load balancing

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Runtime Row/Column Activation Pruning for ReRAM-based processing-in-memory DNN Accelerators 42

Runtime Row/Column Activation Pruning for ReRAM-based Proces...

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42nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

作者： Jiang, Xikun Shen, Zhaoyan Sun, Siqing Yin, Ping Jia, Zhiping Ju, Lei Zhang, Zhiyong Yu, Dongxiao Shandong Univ Sch Comp Sci & Technol Qingdao Peoples R China Cloud Inspur Informat Technol Co Ltd Qingdao Peoples R China Shandong Univ Sch Cyber Sci & Technol Qingdao Peoples R China

ISBN: (纸本)9798350322255

Resistive random access memory (ReRAM)-based processing-in-memory (PIM) DNN accelerators have shown great potential in improving model efficiency and saving energy. To further improve memory and computation efficiency, model weight sparsity has been widely explored in ReRAM-based accelerator designs. However, these optimized accelerators rarely touched the model activation sparsity. In this paper, we observe that there exist plenty sparse rows/columns in the DNN model activation matrix which have negligible effect on accuracy, termed as insensitive rows/columns. Pruning them has little impact on model accuracy but would have significant potential to improve the performance and energy efficiency of DNN accelerators. Therefore, we propose a new ReRAM-based PIM accelerator, named as RapPIM, to take advantage of the model activation sparsity. In RapPIM, we first propose an insensitive activation rows/columns pruning method to search and prune the insensitive rows/columns. Then, we present an activation low-bits skipping strategy and a forward propagation delay hiding strategy to further improve model performance and minimize the latency of activation pruning on forward propagation. Our evaluations with several well-known DNN models show that the RapPIM achieves up to 2.40x speedup and 44.82% power reduction compared with the state-of-the-art ReRAM-based accelerator.

关键词： processing-in-memory ReRAM Activation Pruning Neural Network

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