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检索条件"主题词=processor array"
94 条 记 录,以下是1-10 订阅
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processor array design with FPGA area constraint
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1999年 第3期18卷 253-264页
作者: Fernando, JA Jean, JSN Systran Fed Corp Dayton OH 45432 USA Wright State Univ Dept Comp Sci & Engn Dayton OH 45435 USA
Digital signal processing algorithms with multiple shift-invariant dependence graphs (DG's) can be mapped to field programmable gate array hardware in many different types of systolic processor arrays, Because of ... 详细信息
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processor array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm
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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2011年 第7期22卷 1142-1149页
作者: Ibrahim, Atef Gebali, Fayez Elsimary, Hamed Nassar, Amin Elect Res Inst Dept Microelect Cairo 12622 Egypt Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada Cairo Univ Elect & Elect Commun Dept Cairo 12613 Egypt
This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular ... 详细信息
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processor array architectures for deep packet classification
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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2006年 第3期17卷 241-252页
作者: Gebali, F Rafiq, ANME Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada
This paper presents a systematic technique for expressing a string search algorithm as a regular iterative expression to explore all possible processor arrays for deep packet classification. The computation domain of ... 详细信息
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Simulation of the processor array with reconfigurable bus system on the PRAM
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JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS 1996年 第5期19卷 615-622页
作者: Lin, SS Department of Information and Computer Education National Taiwan Normal University Taipei 106 Taiwan
A processor array with a reconfigurable bus system (abbreviated to PARBS) is a computation model which consists of a processor array and a reconfigurable bus system. It is a very powerful computation model in that man... 详细信息
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Scalable energy-efficient parallel sorting on a fine-grained many-core processor array
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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2020年 第0期138卷 32-47页
作者: Stillmaker, Aaron Bohnenstiehl, Brent Stillmaker, Lucas Baas, Bevan Univ Calif Davis Elect & Comp Engn Dept One Shields Ave Davis CA 95616 USA Calif State Univ Elect & Comp Engn Dept Fresno 2320 E San Ramon Ave Fresno CA 93740 USA
Three parallel sorting applications and two list output protocols for the first phase of an external sort execute on a fine-grained many-core processor array that contains no algorithm-specific hardware acting as a co... 详细信息
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General-purpose 128 x 128 SIMD processor array with integrated image sensor
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ELECTRONICS LETTERS 2006年 第12期42卷 678-679页
作者: Dudek, P. Carey, S. J. Univ Manchester Sch Elect & Elect Engn Manchester M60 1QD Lancs England
A CMOS image sensor/processor chip fabricated in a 0.35 mu m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128 x 128 processing elements. It executes over 20 GOP... 详细信息
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PARALLEL FFT ALGORITHMS USING RADIX-4 BUTTERFLY COMPUTATION ON AN 8-NEIGHBOR processor array
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PARALLEL COMPUTING 1995年 第1期21卷 121-136页
作者: TANNO, K TAKETA, T HORIGUCHI, S JAPAN ADV INST SCI & TECHNOL SCH INFORMAT SCITATUNOKUCHIISHIKAWA 92312JAPAN
Fast Fourier transform (FFT), which has wide and variety application areas, requires very high speed computation. Since parallel processing of FFT is very attractive for high speed FFT computation, many processor arra... 详细信息
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Designing a scalable processor array for recurrent computations
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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1997年 第8期8卷 840-856页
作者: Ganapathy, KN Wah, BW Li, CW UNIV ILLINOIS COORDINATED SCI LAB URBANA IL 61801 USA
In this paper, we study the design of a coprocessor (CoP) to execute efficiently recursive algorithms with uniform dependencies. Our design is based on two objectives: 1) fixed bandwidth to main memory (MM) and 2) sca... 详细信息
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processor array SELF-RECONFIGURATION BY NEURAL NETWORKS
PROCESSOR ARRAY SELF-RECONFIGURATION BY NEURAL NETWORKS
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INTERNATIONAL CONF ON WAFER SCALE INTEGRATION
作者: YIH, JS MAZUMDER, P
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A low-area, high-speed, processor array architecture for field ALU over GF (2m)
A low-area, high-speed, processor array architecture for fie...
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ITI 5th International Conference on Information and Communications Technology
作者: Fayed, M. El-Kharashi, M. Watheq Gebali, F. Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada Mentor Graph Egypt Cairo 11341 Egypt
We propose a novel, low-area, high-speed architecture for the basic operations over GF(2(m)). The proposed architecture is a processor array based, which utilizes the most significant bit multiplication algorithm and ... 详细信息
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