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检索条件"主题词=processor array"
94 条 记 录,以下是1-10 订阅
Scalable energy-efficient parallel sorting on a fine-grained many-core processor array
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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2020年 第0期138卷 32-47页
作者: Stillmaker, Aaron Bohnenstiehl, Brent Stillmaker, Lucas Baas, Bevan Univ Calif Davis Elect & Comp Engn Dept One Shields Ave Davis CA 95616 USA Calif State Univ Elect & Comp Engn Dept Fresno 2320 E San Ramon Ave Fresno CA 93740 USA
Three parallel sorting applications and two list output protocols for the first phase of an external sort execute on a fine-grained many-core processor array that contains no algorithm-specific hardware acting as a co... 详细信息
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An Event-Driven Massively Parallel Fine-Grained processor array
An Event-Driven Massively Parallel Fine-Grained Processor Ar...
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IEEE International Symposium on Circuits and Systems (ISCAS)
作者: Walsh, Declan Dudek, Piotr Univ Manchester Sch Elect & Elect Engn Manchester M13 9PL Lancs England
A multi-core event-driven parallel processor array design is presented. Using relatively simple 8-bit processing cores and a 2D mesh network topology, the architecture focuses on reducing the area occupation of a sing... 详细信息
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An Event-Driven Massively Parallel Fine-Grained processor array
An Event-Driven Massively Parallel Fine-Grained Processor Ar...
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IEEE International Symposium on Circuits and Systems
作者: Declan Walsh Piotr Dudek School of Electrical and Electronic Engineering The University of Manchester UK
A multi-core event-driven parallel processor array design is presented. Using relatively simple 8-bit processing cores and a 2D mesh network topology, the architecture focuses on reducing the area occupation of a sing... 详细信息
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IMAGine: An In-Memory Accelerated GEMV Engine Overlay  34
IMAGine: An In-Memory Accelerated GEMV Engine Overlay
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34th International Conference on Field-Programmable Logic and Applications (FPL)
作者: Kabir, M. D. Arafat Kamucheka, Tendayi Fredricks, Nathaniel Mandebi, Joel Bakos, Jason Huang, Miaoqing Andrews, David Univ Arkansas Dept Elect Engn & Comp Sci Fayetteville AR 72701 USA Univ South Carolina Dept Comp Sci & Engn Columbia SC USA Adv Micro Devices Inc AMD Santa Clara CA USA
processor-in-Memory (PIM) overlays and alternative reconfigurable tile fabrics have been proposed to eliminate the von Neumann bottleneck and enable processing performance to scale with BRAM capacity. The performance ... 详细信息
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Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices
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ALEXANDRIA ENGINEERING JOURNAL 2022年 第12期61卷 13079-13087页
作者: Ibrahim, Atef Gebali, Fayez Prince Sattam Bin Abdulaziz Univ Alkharj Coll Comp Engn & Sci Comp Engn Dept Al Kharj Saudi Arabia Univ Victoria ECE Dept Victoria BC Canada
Adoption of IoT technology without considering its security implications may expose network systems to a variety of security breaches. In network systems, IoT edge devices are a major source of security risks. Impleme... 详细信息
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Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays  31
Making BRAMs Compute: Creating Scalable Computational Memory...
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31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
作者: Kabir, Md Arafat Hollis, Joshua Panahi, Atiyehsadat Bakos, Jason Huang, Miaoqing Andrews, David Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA Univ South Carolina Dept Comp Sci & Comp Engn Columbia SC USA Cadence Design Syst Dept Comp Sci & Comp Engn San Jose CA USA
The increasing density of distributed BRAMs diffused throughout modern Field Programmable Gate arrays (FPGAs) is ideal for forming processor in/near memory architectures. This breaks the traditional von Neumann memory... 详细信息
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A Scalable JPEG Encoder on a Many-Core array  16
A Scalable JPEG Encoder on a Many-Core Array
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16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
作者: Abbott, Thomas Baas, Bevan Univ Calif Davis ECE Dept Davis CA 95616 USA
JPEG is a widely-used image compression algorithm. A 31-core JPEG encoder and a scalable family of JPEG encoders were developed for a fine-grain many-core processor array and are measured on the 32 nm KiloCore chip. T... 详细信息
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A mathematical programming method for constructing the shortest interconnection VLSI arrays
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INTEGRATION-THE VLSI JOURNAL 2021年 81卷 167-174页
作者: Ding, Hao Qian, Junyan Zhao, Lingzhong Zhai, Zhongyi Guilin Univ Elect Technol Guangxi Key Lab Trusted Software Guilin 541004 Peoples R China Guangxi Normal Univ Guangxi Key Lab Multisource Informat Min & Secur Guilin 541004 Peoples R China
Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty ... 详细信息
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A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications  31
A Customizable Domain-Specific Memory-Centric FPGA Overlay f...
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31st International Conference on Field-Programmable Logic and Applications (FPL)
作者: Panahi, Atiyehsadat Balsalama, Suhail Ishimwe, Ange-Thierry Mbongue, Joel Mandebi Andrews, David Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA Univ Florida Dept Comp Sci & Comp Engn Fayetteville AR USA
This paper presents an overview and performance analysis of a software-programmable domain-customizable System-on-Chip (SoC) overlay for low-latency inferencing of variable and low-precision Machine Learning (ML) netw... 详细信息
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Low Power Multiple Object Tracking and Counting using a SCAMP Cellular processor array
Low Power Multiple Object Tracking and Counting using a SCAM...
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13th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA)
作者: Barr, David R. W. Carey, Stephen J. Dudek, Piotr Univ Manchester Sch Elect & Elect Engn Manchester M13 9PL Lancs England
A low-power demonstration system using a SCAMP-3 vision chip to track and count multiple objects with unpredictable trajectories is presented. The system can track as many discrete objects that can fit into its visual... 详细信息
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