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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Walsh, Declan Dudek, Piotr Univ Manchester Sch Elect & Elect Engn Manchester M13 9PL Lancs England

ISBN: (纸本)9781479983919

A multi-core event-driven parallel processor array design is presented. Using relatively simple 8-bit processing cores and a 2D mesh network topology, the architecture focuses on reducing the area occupation of a single processor core. A large number of these processor cores can be implemented on a single integrated chip to create a MIMD architecture capable of providing a powerful processing performance. Each processor core is an event-driven processor which can enter an idle mode when no data is changing locally. An 8 x 8 prototype processor array is implemented in a 65 nm CMOS process in 1,875 mu m x 1,875 mu m. This processor array is capable of performing 5.12 GOPS operating at 80 MHz with an average power consumption of 75.4 mW.

关键词： MIMD many-core event-driven fine-grained processor array parallel processing scalable

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NEW processor array ARCHITECTURE FOR SCALABLE RADIX 8 MONTGOMERY MODULAR MULTIPLICATION ALGORITHM

NEW PROCESSOR ARRAY ARCHITECTURE FOR SCALABLE RADIX 8 MONTGO...

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24th Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Ibrahim, Atef Gebali, Fayez Elsimary, Hamed Nassar, Amin ERI Dept Microelect Cairo Egypt Univ Victoria Victoria BC V8W 2Y2 Canada Cairo Univ Cairo Egypt

ISBN: (纸本)9781424497898

This paper presents a new processor array architecture for scalable radix 8 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architectures extracted by G. Todorov. Moreover, the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. By analyzing this architecture, we found that it has a better performance - in terms of area, speed, and power consumption-than the previous radix 8 architecture extracted by G. Todorov.

关键词： processor array Montgomery multiplication Scalability Cryptography Secure communications Low power modular multipliers

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A high-speed, low-area processor array architecture for multiplication and squaring over

A high-speed, low-area processor array architecture for mult...

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2nd International Design and Test Workshop

作者： Fayed, Mohamed A. El-Kharashi, M. Watheq Gebali, Fayez Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada Mentor Graph Egypt Cairo 11341 Egypt

ISBN: (纸本)9781424418244

We propose a novel, high-speed, low-area architecture for multiplication and squaring over GF(2(m)). The proposed architecture is processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. Our architecture requires only m processing elements as compared to m(2)/2 for the best previous design. We use NIST-recommended polynomials, which makes our design secure and more suitable for cryptographic engines. The proposed architecture is implemented or m is an element of {163, 283, 571} on a Xilinx XC2V4000-6 device to verify its functionality and measure its performance. We achieve a frequency of 264 MHz, which allows the architecture to calculate GF(2(163)) multiplication in 640 ns and squaring in 57 ns.

关键词： Elliptic Curve Cryptography (ECC) finite or Galois Field GF(2(m)) GF(2(m)) arithmetic GF(2(m)) multiplication GF(2(m)) squaring processor array

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Low Power Multiple Object Tracking and Counting using a SCAMP Cellular processor array

Low Power Multiple Object Tracking and Counting using a SCAM...

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13th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA)

作者： Barr, David R. W. Carey, Stephen J. Dudek, Piotr Univ Manchester Sch Elect & Elect Engn Manchester M13 9PL Lancs England

ISBN: (纸本)9781467302890

A low-power demonstration system using a SCAMP-3 vision chip to track and count multiple objects with unpredictable trajectories is presented. The system can track as many discrete objects that can fit into its visual field. The compact, self-contained hardware consists of a battery, an ARM Cortex-M3 co-processor, and the sensor/processor array device. The tracking algorithm is performed entirely by the processor array and the complete system draws 7.3mA during operation.

关键词： Vision Chip processor array SIMD Smart Sensors Multiple Object Tracking

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Simulation of the processor array with reconfigurable bus system on the PRAM

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JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS 1996年第5期19卷 615-622页

作者： Lin, SS Department of Information and Computer Education National Taiwan Normal University Taipei 106 Taiwan

A processor array with a reconfigurable bus system (abbreviated to PARBS) is a computation model which consists of a processor array and a reconfigurable bus system. It is a very powerful computation model in that many problems can be solved efficiently. The power of a computation model usually indicates how fast a problem can be solved under that model. In [16], Wang and Chen have shown that the two-dimensional PARBS is at least as powerful as the PRAM (parallel random access machine). That is, if a problem can be solved in O(f(n)) time on the PRAM with n processors and m memory cells, it can also be solved in O(f(n)) time on the two-dimensional PARBS with n*m processors. The reverse assertion has not been proven yet. The difficulty arises from the great flexibility in the configurations of reconfigurable system. In this paper, we show that a restricted version of the PARBS, called ORTHOGONAL PARBS, which includes all one-dimensional PARBS with two-neighbor connections and many two-dimensional PARBS with four-neighbor connections used by some researchers, can be simulated accordingly on the SUM CRCW PRAM. That is, if a problem can be solved in O(f(n)) time on the ORTHOGONAL PARBS with n processors, it can also be solved in O(f(n)) time and O(n) memory cells on the SUM CRCW PRAM.

关键词： computation model parallel random access machine processor array reconfigurable bus system

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One-dimensional processor array system for fast analysis of tissue motion in ultrasonogram

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JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 1999年第5B期38卷 3385-3387页

作者： Yamada, M Fukuzawa, M Kitsunezuka, Y Kyoto Inst Technol Dept Elect & Informat Sci Sakyo Ku Kyoto 6068585 Japan Saiseikai Hyogo Ken Hosp Dept Pediat Kita Ku Kobe Hyogo 6511302 Japan

A one-dimensional processor array system using 256 pieces of 8 bit processor elements (PEs) is proposed, by which we can easily deal with ultrasound-echo moving images at the video rate (33 ms/frame) for medical diagnosis. The PEs used are the socalled "single instruction stream multiple data stream" (SIMD) type of parallel processors, which simultaneously perform the same operation upon instruction provided from a control processor: The data transfer rates for an image with 256x 256 pixels are 10.24 GB/s (5,300 frames/33 ms) between PEs and internal memories and 1.28 GB/s (660 frames/33 ms) between internal and external memories, which are sufficient to deal with ultrasound-echo moving images at the video rate without any bus bottleneck, as seen frequently in single processor systems. As an example, the real-time performance of the one-dimensional processor array system is confirmed by detecting artery pulsation from a series of ultrasound-echo moving images of a neonatal head.

关键词： ultrasonogram moving image tissue motion processor array SIMD medical diagnosis

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Probability of correctness of processor-array outputs using periodic concurrent error detection

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IEEE TRANSACTIONS ON RELIABILITY 1996年第2期45卷 285-296页

作者： Chen, PP Mourad, AN Fuchs, WK UNIV ILLINOIS COORDINATED SCI LABURBANAIL 61801 AT&T BELL LABS HOLMDELNJ 07733

processor arrays, featuring modularity, regular interconnection, and high parallelism, are well suited for VLSI/WSI implementation and specific applications with high computational requirements, Error detection & recovery are important for some applications of processor arrays, Concurrent error detection (CED) techniques, which check normal system operations, are designed to detect errors caused by transient & intermittent faults, However, CED techniques typically suffer from costly hardware penalties or performance costs. This paper describes the Periodic Application of Concurrent Error Detection (PACED) technique which allows the performance costs incurred through the use of time-redundant CED in processor array architectures to be reduced, The application of CED is varied in both time & space to provide probabilistic detection of errors in processor arrays, The probability of correctness of outputs from processor arrays is studied, Formulae are derived that predict, upon error detection, the amount of possibly erroneous output, for single processors, linear arrays, and 2-dimensional mesh processor arrays, The results indicate that the error coverage can be surprisingly high when PACED is applied in processor arrays, eg, 95% for checking performed 50% of the time.

关键词： fault tolerance concurrent error detection processor array error analysis

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An Event-Driven Massively Parallel Fine-Grained processor array

An Event-Driven Massively Parallel Fine-Grained Processor Ar...

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IEEE International Symposium on Circuits and Systems

作者： Declan Walsh Piotr Dudek School of Electrical and Electronic Engineering The University of Manchester UK

ISBN: (纸本)9781479983926

A multi-core event-driven parallel processor array design is presented. Using relatively simple 8-bit processing cores and a 2D mesh network topology, the architecture focuses on reducing the area occupation of a single processor core. A large number of these processor cores can be implemented on a single integrated chip to create a MIMD architecture capable of providing a powerful processing performance. Each processor core is an event-driven processor which can enter an idle mode when no data is changing locally. An 8 × 8 prototype processor array is implemented in a 65 nm CMOS process in 1,875 μm × 1,875 μm. This processor array is capable of performing 5.12 GOPS operating at 80 MHz with an average power consumption of 75.4 mW.

关键词： MIMD many-core event-driven fine-grained processor array parallel processing scalable

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A Low-Area, High-Speed, processor array Architecture for Field ALU over GF (2{sup}m)

A Low-Area, High-Speed, Processor Array Architecture for Fie...

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5th International Conference on Information & Communications Technology

作者： M. Fayed M. Watheq El-Kharashi F. Gebali Department of Electrical and Computer Engineering University of Victoria Victoria BC Canada Mentor Graphics Egypt Cairo Egypt

We propose a novel, low-area, high-speed architecture for the basic operations over GF(2{sup}m). The proposed architecture is a processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. We use the National Institute of Standard and Technology recommended polynomials, which makes our design secure and more suitable for cryptographic applications. The proposed architecture is implemented for m∈{163,283,571} on a Xilinx XC2V4000 device to verify its functionality and measure its performance. We achieve a frequency of 264 MHz, which allows the architecture to calculate GF(2{sup}163) multiplication in 640ns and inversion in 14.357μs.

关键词： Elliptic Curve Cryptography (ECC) Finite or Galois Field GF(2{sup}m) GF(2{sup}m) Arithmetic GF(2{sup}m) Inversion GF(2{sup}m) Multiplication GF(2{sup}m) Squaring processor array

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List ranking on processor arrays

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JOURNAL OF SYSTEMS AND SOFTWARE 2000年第2期55卷 185-192页

作者： Çam, H King Fahd Univ Petr & Minerals Dept Comp Engn Dhahran 31261 Saudi Arabia

List ranking finds for each cell in a linked list the number of cells that precede it in the list. This paper presents a work-efficient list-ranking algorithm for fine-grained processor arrays. This algorithm runs on an array of n/ log(2) n processors with the expected run-time of O(log(2) n). As list ranking is highly communication intensive, the proposed algorithm is able to reduce communication cost among processors by assigning sublists, instead of arbitrary cells, of a linked list to each processor. The proposed algorithm is also capable of keeping all processors busy during the whole list-ranking process in order to utilize all processors efficiently. (C) 2000 Elsevier Science Inc. All rights reserved.

关键词： parallel algorithm list ranking work-efficient PRAM algorithm processor array

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