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Topographic implementation of particle filters on cellular processor arrays

SIGNAL PROCESSING 2013年第7期93卷 1853-1863页

作者： Horvath, Andras Rasonyi, Miklos Pezmany Peter Catholic Univ Fac Informat Technol H-1444 Budapest Hungary Univ Edinburgh Sch Math Edinburgh EH9 3JZ Midlothian Scotland

Particle filters are a state-of-the-art method for the state estimation of non-linear stochastic systems. Recent many-core architectures and cellular processor arrays offer a new paradigm for algorithm development, which provides not only high performance, but also theoretical advances for parallel implementations. We have developed a new variant of the particle filter algorithm, which suits ideally implementation on a cellular processor array. The new algorithm often performs better than the classical one and a significant gain in running time can be achieved, especially when there is a large number of particles to be simulated. (C) 2012 Elsevier B.V. All rights reserved.

关键词： Hidden Markov process Non-linear filtering Sequential Monte Carlo method Particle filter processor array Cellular neural networks

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Constructing Compact Logical arrays under Flexible Rerouting Schemes

Constructing Compact Logical Arrays under Flexible Rerouting...

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15th IEEE International Conference on High Performance Computing and Communications (HPCC) /11th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC)

作者： Jiang, Guiyuan Wu, Jigang Sun, Jizhou Gao, Yiyi Tianjin Univ Sch Comp Sci & Technol Tianjin 300072 Peoples R China Tianjin Polytech Univ Sch Comp Sci & Software Engn Tianjin 300387 Peoples R China

ISBN: (纸本)9780769550886

In a multiprocessor array, some processing elements (PEs) fail to function normally due to hardware defects or soft faults caused by overheating, overload or occupancy by other running applications. Fault-tolerant reconfiguration reorganizes fault-free PEs to a logical topology by changing the interconnection among PEs. This paper develops an efficient heuristic algorithm, denoted as CLA, to construct maximum logical array (MLA) with short interconnects under flexible rerouting schemes. In CLA, two MLAs are generated using an existing algorithm FLX, and are then utilized to produce the target logical array. The middle column of the target logical array is generated by forming the straightest column on an area bounded by two logical columns of the two MLAs. Other columns are generated by forming compact columns on relative areas. The problem of finding a compact logical column on an given area is solved by modeling it as a shortest path problem on a directed graph with weights where both vertices and edges of the graph are associated with nonnegative costs. Experimental results validate the efficiency of the the proposed algorithm. For 128 x 128 host arrays with 40% unavailable PEs, the proposed approach improves existing algorithm up to 44% in terms of interconnection length. In addition, the improvement increases with the increasing fault density, implying that CLA is more scalable than the existing algorithm.

关键词： processor array reconfiguration compact array interconnection length interconnection networks

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Multithread Reconfiguration Algorithm for Mesh-connected processor arrays

Multithread Reconfiguration Algorithm for Mesh-connected Pro...

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13th International Conference on Parallel and Distributed Computing, Applications, and Technologies (PDCAT)

作者： Shen, Yuze Wu, Jigang Jiang, Guiyuan Tianjin Polytech Univ Sch Comp Sci & Software Engn Tianjin 300387 Peoples R China Tianjin Univ Sch Comp Sci & Technol Tianjin 300072 Peoples R China

ISBN: (纸本)9780769548791

Mesh-connected processor array is a popular architecture used in parallel processing. Extensive studies have been conducted on reconfiguration algorithms for the processor arrays with faults, but few work is on parallel algorithm to accelerate the reconfiguration. This paper presents a fast algorithm to reconfigure two dimensional mesh-connected processor arrays with faults. A traditional algorithm is successfully accelerated in the manner of multithread, without loss of harvest. The proposed algorithm reconfigures the processor array with the mechanics of route distance in order to avoid the routing errors. Simulation results show that the proposed algorithm can accelerate the reconfiguration nearly by 15 times on a 64 x 64 array in comparison to the traditional algorithm cited in this paper.

关键词： Mesh processor array reconfiguration fault tolerance parallel routing

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Locating High Speed Multiple Objects using a SCAMP-5 Vision-Chip

Locating High Speed Multiple Objects using a SCAMP-5 Vision-...

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13th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA)

作者： Carey, Stephen J. Barr, David R. W. Wang, Bin Lopich, Alexey Dudek, Piotr Univ Manchester Sch Elect Engn & Elect Manchester M13 7PL Lancs England

ISBN: (纸本)9781467302890

Presented in this paper is a demonstration system that uses a low-power SCAMP-5 256x256 vision-chip to locate and count multiple objects moving at high speed along arbitrary trajectories. The hardware consists of a SCAMP-5 IC, its power supply system and a Xilinx Spartan3 controller. At 100,000fps, the SCAMP-5 chip can locate and readout the coordinates of a single closed-shaped object amongst clutter. At 25,000fps, the IC can readout the coordinates of 5 objects.

关键词： Vision Chip processor array SIMD Smart Sensors

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IRIS RECOGNITION USING ADABOOST AND LEVENSHTEIN DISTANCES

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INTERNATIONAL JOURNAL OF PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE 2012年第2期26卷 1266001-1266001页

作者： Climent, Joan Hexsel, Roberto A. Univ Politecn Cataluna Comp Engn & Automat Control Dept Barcelona Spain Univ Fed Parana UFPR Dept Informat BR-80060000 Curitiba Parana Brazil

This paper presents an efficient IrisCode classifier, built from phase features which uses AdaBoost for the selection of Gabor wavelets bandwidths. The final iris classifier consists of a weighted contribution of weak classifiers. As weak classifiers we use three-split decision trees that identify a candidate based on the Levenshtein distance between phase vectors of the respective iris images. Our experiments show that the Levenshtein distance has better discrimination in comparing IrisCodes than the Hamming distance. Our process also differs from existing methods because the wavelengths of the Gabor filters used, and their final weights in the decision function, are chosen from the robust final classifier, instead of being fixed and/or limited by the programmer, thus yielding higher iris recognition rates. A pyramidal strategy for cascading filters with increasing complexity makes the system suitable for real-time operation. We have designed a processor array to accelerate the computation of the Levenshtein distance. The processing elements are simple basic cells, interconnected by relatively short paths, which makes it suitable for a VLSI implementation.

关键词： Iris recognition AdaBoost biometrics Levenshtein distance string matching processor array

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A low-area, high-speed, processor array architecture for field ALU over GF (2^m)

A low-area, high-speed, processor array architecture for fie...

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ITI 5th International Conference on Information and Communications Technology

作者： Fayed, M. El-Kharashi, M. Watheq Gebali, F. Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada Mentor Graph Egypt Cairo 11341 Egypt

ISBN: (纸本)9781424414307

We propose a novel, low-area, high-speed architecture for the basic operations over GF(2(m)). The proposed architecture is a processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. We use the National Institute of Standard and Technology recommended polynomials, which makes our design secure and more suitable for cryptographic applications. The proposed architecture is implemented for m is an element of {163,283,571} on a Xilinx XC2V4000 device to verify its functionality and measure its performance. We achieve a frequency of 264 MHz, which allows the architecture to calculate GF(2163) multiplication in 640ns and inversion in 14..357 mu s.

关键词： elliptic curve cryptography (ECC) finite or galois field GF(2(m)) GF(2(m)) arithmetic GF(2(m)) inversion GF(2(m)) multiplication GF(2(m)) squaring processor array

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A high-speed, high-radix, processor array architecture for real-time elliptic curve cryptography over GF(2^m)

A high-speed, high-radix, Processor Array architecture for r...

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7th IEEE International Symposium on Signal Processing and Information Technology

作者： Fayed, Mohamed A. EI-Kharashi, M. Watheq Gebali, Fayez Univ Victoria Dept Elec & Comp Engn Victoria BC V8W 3P6 Canada Mentor Graphics Egypt Cairo 11341 Egypt

ISBN: (纸本)9781424418343

This paper presents a high-radix elliptic curve cryptographic architecture that performs a scalar multiple of an elliptic curve point operations over GF(2(m)). The proposed architecture is based on a new algorithm, which is a modified version of the sliding window scalar multiplication algorithm. We speed-up the scalar multiplication by merging the point doubling and adding operations into a single step, which decreases the scalar multiplication critical path delay at the expense of a larger Look-Up Table. The proposed architecture utilizes an optimized processor array-based field ALU that efficiently implements addition, squaring, multiplication and division over GF(2(m)). The proposed architecture is implemented for m is an element of {163, 283, 571} on a Xilinx XC4VFX100-12 device. We achieved a frequency of 253 MHz, which allows the architecture to calculate GF (2(163)) scalar multiplication for radix 2(8) in 9 mu s. Our results for GF(2(163)) show a speed-up that ranges from 1.5 to 326 in comparison to previous FPGA implementations and a speed-up ranges from 1.1 to 5.6 in comparison to previous ASIC implementations.

关键词： ALU design elliptic curve cryptography (ECC) processor array public key cryptosystems scalar multiplication

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A high-speed, low-area processor array architecture for multiplication and squaring over

A high-speed, low-area processor array architecture for mult...

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2nd International Design and Test Workshop

作者： Fayed, Mohamed A. El-Kharashi, M. Watheq Gebali, Fayez Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada Mentor Graph Egypt Cairo 11341 Egypt

ISBN: (纸本)9781424418244

We propose a novel, high-speed, low-area architecture for multiplication and squaring over GF(2(m)). The proposed architecture is processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. Our architecture requires only m processing elements as compared to m(2)/2 for the best previous design. We use NIST-recommended polynomials, which makes our design secure and more suitable for cryptographic engines. The proposed architecture is implemented or m is an element of {163, 283, 571} on a Xilinx XC2V4000-6 device to verify its functionality and measure its performance. We achieve a frequency of 264 MHz, which allows the architecture to calculate GF(2(163)) multiplication in 640 ns and squaring in 57 ns.

关键词： Elliptic Curve Cryptography (ECC) finite or Galois Field GF(2(m)) GF(2(m)) arithmetic GF(2(m)) multiplication GF(2(m)) squaring processor array

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processor array architectures for deep packet classification

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2006年第3期17卷 241-252页

作者： Gebali, F Rafiq, ANME Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada

This paper presents a systematic technique for expressing a string search algorithm as a regular iterative expression to explore all possible processor arrays for deep packet classification. The computation domain of the algorithm is obtained and three affine scheduling functions are presented. The technique allows some of the algorithm variables to be pipelined while others are broadcast over system-wide buses. Nine possible processor array structures are obtained and analyzed in terms of speed, area, power, and I/O timing requirements. Time complexities are derived analytically and through extensive numerical simulations. The proposed designs exhibit optimum speed and area complexities. The processor arrays are compared with previously derived processor arrays for the string matching problem.

关键词： processor array string search deep packet classification parallel hardware

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A Low-Area, High-Speed, processor array Architecture for Field ALU over GF (2{sup}m)

A Low-Area, High-Speed, Processor Array Architecture for Fie...

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5th International Conference on Information & Communications Technology

作者： M. Fayed M. Watheq El-Kharashi F. Gebali Department of Electrical and Computer Engineering University of Victoria Victoria BC Canada Mentor Graphics Egypt Cairo Egypt

We propose a novel, low-area, high-speed architecture for the basic operations over GF(2{sup}m). The proposed architecture is a processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. We use the National Institute of Standard and Technology recommended polynomials, which makes our design secure and more suitable for cryptographic applications. The proposed architecture is implemented for m∈{163,283,571} on a Xilinx XC2V4000 device to verify its functionality and measure its performance. We achieve a frequency of 264 MHz, which allows the architecture to calculate GF(2{sup}163) multiplication in 640ns and inversion in 14.357μs.

关键词： Elliptic Curve Cryptography (ECC) Finite or Galois Field GF(2{sup}m) GF(2{sup}m) Arithmetic GF(2{sup}m) Inversion GF(2{sup}m) Multiplication GF(2{sup}m) Squaring processor array

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