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General-purpose 128 x 128 SIMD processor array with integrated image sensor

ELECTRONICS LETTERS 2006年第12期42卷 678-679页

作者： Dudek, P. Carey, S. J. Univ Manchester Sch Elect & Elect Engn Manchester M60 1QD Lancs England

A CMOS image sensor/processor chip fabricated in a 0.35 mu m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128 x 128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 4 10 cells/mm(2). Performance and accuracy measurement results are given.

关键词： .circuitry SIMD General-purpose APE processor array vision chip SCAMP

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Minimizing interconnect length on reconfigurable meshes

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中国高等学校学术文摘·计算机科学 2009年第3期3卷 315-321页

作者： Jigang WU Thambipillai SRIKANTHAN Kai WANG School of Computer Science and Software Tianjin Polytechnic University Tianjin 300160 China School of Computer Engineering Nanyang Technological University Singapore 639798 Singapore School of Computer Engineering Nanyang Technological University Singapore 639798 Singapore

Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter inter-connect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially gen-erates the middle (|k/2|th) logical column and then makes it nearly straight for the MLA with k logical columns. A dy-namic programming approach is presented to compact other logical columns toward the middle logical column, result-ing in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experi-mental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.

关键词： Mesh reconfiguration processor array routing algorithm

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Application-specific processor architecture: Then and now

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第1-2期53卷 197-215页

作者： Cappello, Peter Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago. We then observe that those same design forces now are bearing down on the architects of contemporary general-purpose processors, who consequently are producing general-purpose processors whose architectural features are increasingly similar to those of systolic arrays. We then describe some economic and technological forces that are changing the landscape of architectural research. At base, they are the increasing complexity of technology and applications, the fragmenting of the general-purpose processor market, and the judicious use hardware configurability. We describe a 2D architectural taxonomy, identifying what, we believe, to be a "sweet spot" for architectural research.

关键词： application-specific processor computer architecture field-programmable gate array FPGA general-purpose processor processor array systolic array taxonomy

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Application-specific processor architecture: Then and now

Application-specific processor architecture: Then and now

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17th IEEE International Conference on Application-Specific Systems, Architectures and processors

作者： Cappello, Peter Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

关键词： application-specific processor computer architecture field-programmable gate array FPGA general-purpose processor processor array systolic array taxonomy

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Communication-conscious mapping of regular nested loop programs onto massively parallel processor arrays

Communication-conscious mapping of regular nested loop progr...

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18th IASTED International Conference on Parallel and Distributed Computing and Systems

作者： Siegel, Sebastian Merker, Renate Hannig, Frank Teich, Juergen Tech Univ Dresden Inst Circuits & Syst D-01062 Dresden Germany Univ Erlangen Nurnberg Dept Comp Sci 12 D-91058 Erlangen Germany

ISBN: (纸本)9780889866386

Methods for an efficient mapping of algorithms to parallel architectures are of utmost importance because many state-of-the-art embedded digital systems deploy parallelism to increase their computational power. This paper deals with the mapping of loop programs onto processor arrays implemented in an FPGA or available as (reconfigurable) coarsegrained processor architectures. Most existing work is closely related to approaches from the DSP domain and is not able to exploit the full parallelism of a given algorithm and the computational potential of a typical 2-dimensional array. In contrast, we present a mapping methodology which incorporates many important parameters of the target architecture in one approach. These are: number of processing elements, resources of the data path and memory within a processing element, and interconnection within the processor array. Based on these parameters, we formulate an optimization problem whose solution specifies an efficient mapping of an algorithm to the target architecture. We can optimize for speed of the algorithm and/or hardware cost caused by the communication and computation resources of the architecture.

关键词： processor array interconnection data path hardware mapping integer linear programming

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Optimization of communication cost within processor arrays caused by I/O

Optimization of communication cost within processor arrays c...

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18th IASTED International Conference on Parallel and Distributed Computing and Systems

作者： Siegel, Sebastian Merker, Renate Tech Univ Dresden Inst Circuits & Syst D-01062 Dresden Germany

ISBN: (纸本)9780889866386

Fine grain parallel architectures such as processor arrays (PAs) play an important role in the acceleration of applications which demand high processing capabilities. Methods for the mapping of compute-intensive algorithms to PAs often neglect an efficient routing of input and output (I/O). We formulate an integer linear program (ILP) with the objective to minimize the cost of channels and registers within the PA which are required to route the I/O. This optimization problem is integrated in our framework for the design of PAs. There we use partitioning to map algorithms to PAs. I/O is caused by the algorithm itself and in partitioning by the intermediate data because of the sequential execution of the partitions. The ILP for the routing of the I/O can be combined with an optimization problem which considers the efficient routing of the data dependencies of the algorithm within the PA. We demonstrate the combined approach on the edge detection algorithm.

关键词： processor array input/output interconnection partitioning integer linear programming

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Solving the longest common subsequence (LCS) problem using the associative ASC processor with reconfigurable 2D mesh

Solving the longest common subsequence (LCS) problem using t...

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18th IASTED International Conference on Parallel and Distributed Computing and Systems

作者： Virdi, Sabegh Singh Wang, Hong Walker, Robert A. Kent State Univ Dept Comp Sci Kent OH 44242 USA

ISBN: (纸本)9780889866386

As new genes are sequenced, it is common for molecular biologists to compare the new gene's DNA to known sequences. One simple form of DNA sequence comparison is done by solving the Longest Common Subsequence (LCS) problem. In this paper, we propose a parallel algorithm and specialized FPGA-based processor (the associative ASC processor with reconfigurable 2D mesh) to solve the exact and approximate match LCS problems. This solution uses inexpensive hardware and can be reconfigured as new analysis techniques are developed, making it particularly attractive for processing biosequences.

关键词： SIMD associative computing processor array longest common subsequence sequence analysis biosequences

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Implementing a multiple-instruction-stream associative MASC processor

Implementing a multiple-instruction-stream associative MASC ...

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18th IASTED International Conference on Parallel and Distributed Computing and Systems

作者： Wang, Hong Walker, Robert A. Univ Toledo Dept Engn Technol 2801 W Bancroft St Toledo OH 43606 USA Kent State Univ Dept Comp Sci Kent OH 44242 USA

ISBN: (纸本)9780889866386

For search-intensive applications such as data mining and bioinformatics, a SIMD processor array on a Chip may be an effective architecture, and if the application is control-intensive, a Multiple SIMD (MSIMD) architecture may further increase processor utilization. In this paper, we describe the implementation of an associative MSIMD architecture on the MASC processor. The MASC processor implemented using FPGAs, is easily scalable, and dynamically assigns tasks to Processing Elements as the program executes.

关键词： SIMD multiple SIMD (MSIMD) associative computing processor array processor design FPGA

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Reconfiguration classes and an optimal reconfiguration method within a reconfiguration class

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2002年第12期E85D卷 1909-1917页

作者： Shigei, N Miyajima, H Kagoshima Univ Kagoshima 8900065 Japan

This paper considers a reconfiguration problem on a processor array model based on single-and-half-track switches, which is proposed for a fault tolerance technique at the fabrication time. The focus of this paper is to achieve the optimal reconfigurability, which means that whenever there exists a solution for successful reconfiguration, the designed method can find the solution. The paper consists of two parts. In the first part, we show two essential constraints that have been assumed in most of the previous studies, and make four reconfiguration classes that differ in the assumed essential constraints. Then, we present some inclusion relations among the four reconfiguration classes. As a result, it becomes clear that the most restrictive class including most of the previous methods never achieves the truly optimal reconfigurability. In the second part, we present a reconfiguration method based on sequential routing (RMSR). Although the worst-case time complexity of the RMSR is exponential in the number of processing elements, the reconfigurability of the RMSR is optimal within the most restrictive reconfiguration class. The effectiveness of the RMSR is shown by a computer simulation.

关键词： processor array reconfiguration fault tolerant reconfiguration classes inclusion relation

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Experimental checking of fault susceptibility in a parallel algorithm

Experimental checking of fault susceptibility in a parallel ...

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International Conference on Parallel Computing in Electrical Engineering (PAR ELEC 2002)

作者： Derezinska, A Sosnowski, J Warsaw Univ Technol Inst Comp Sci PL-00665 Warsaw Poland

ISBN: (纸本)0769517307;0769517315

The paper deals with the problem of analyzing fault, susceptibility of a parallel algorithm designed for multiprocessor array (MIMD structure). This algorithm realizes quite complex communication protocol in the system. We present an original methodology of the analysis based on the use of software implemented fault injector. The considered algorithm is modeled as a multithreaded application. The experiment set up an I results are presented and commented The performed experiments proved relatively high natural robustness of the analyzed algorithm and showed further possibilities of its improvement.

关键词： parallel algorithm fault injection multithreaded application processor array

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