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18th IASTED International Conference on Parallel and Distributed Computing and Systems

作者： Siegel, Sebastian Merker, Renate Hannig, Frank Teich, Juergen Tech Univ Dresden Inst Circuits & Syst D-01062 Dresden Germany Univ Erlangen Nurnberg Dept Comp Sci 12 D-91058 Erlangen Germany

ISBN: (纸本)9780889866386

Methods for an efficient mapping of algorithms to parallel architectures are of utmost importance because many state-of-the-art embedded digital systems deploy parallelism to increase their computational power. This paper deals with the mapping of loop programs onto processor arrays implemented in an FPGA or available as (reconfigurable) coarsegrained processor architectures. Most existing work is closely related to approaches from the DSP domain and is not able to exploit the full parallelism of a given algorithm and the computational potential of a typical 2-dimensional array. In contrast, we present a mapping methodology which incorporates many important parameters of the target architecture in one approach. These are: number of processing elements, resources of the data path and memory within a processing element, and interconnection within the processor array. Based on these parameters, we formulate an optimization problem whose solution specifies an efficient mapping of an algorithm to the target architecture. We can optimize for speed of the algorithm and/or hardware cost caused by the communication and computation resources of the architecture.

关键词： processor array interconnection data path hardware mapping integer linear programming

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Multithread Reconfiguration Algorithm for Mesh-connected processor arrays

Multithread Reconfiguration Algorithm for Mesh-connected Pro...

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13th International Conference on Parallel and Distributed Computing, Applications, and Technologies (PDCAT)

作者： Shen, Yuze Wu, Jigang Jiang, Guiyuan Tianjin Polytech Univ Sch Comp Sci & Software Engn Tianjin 300387 Peoples R China Tianjin Univ Sch Comp Sci & Technol Tianjin 300072 Peoples R China

ISBN: (纸本)9780769548791

Mesh-connected processor array is a popular architecture used in parallel processing. Extensive studies have been conducted on reconfiguration algorithms for the processor arrays with faults, but few work is on parallel algorithm to accelerate the reconfiguration. This paper presents a fast algorithm to reconfigure two dimensional mesh-connected processor arrays with faults. A traditional algorithm is successfully accelerated in the manner of multithread, without loss of harvest. The proposed algorithm reconfigures the processor array with the mechanics of route distance in order to avoid the routing errors. Simulation results show that the proposed algorithm can accelerate the reconfiguration nearly by 15 times on a 64 x 64 array in comparison to the traditional algorithm cited in this paper.

关键词： Mesh processor array reconfiguration fault tolerance parallel routing

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Reconfigurations for processor arrays with Faulty Switches and Links 15

Reconfigurations for Processor Arrays with Faulty Switches a...

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2015 15th IEEE ACM International Symposium on Cluster Cloud and Grid Computing (CCGrid 2015)

作者： Wu, Jigang Zhu, Longting He, Peilan Jiang, Guiyuan Guangdong Univ Technol Sch Comp Sci & Technol Guangzhou 510006 Guangdong Peoples R China Tianjin Polytech Univ Sch Comp Sci & Software Engn Tianjin 300387 Peoples R China Tianjin Univ Sch Comp Sci & Technol Tianjin 300072 Peoples R China

ISBN: (纸本)9781479980062

Large scale multiprocessor array suffers from frequent hardware defects or soft faults due to overheating, overload or occupancy by other running applications. To obtain fault-free logical array, reconfiguration techniques are proposed to reuse the fault-free PEs by changing the interconnection among PEs. Previous research has worked on this topic but assume that switches and links are fault-free. In this paper, we consider faults not only on the processing elements (PEs) but also on the switches and links, and develop efficient algorithms to construct as large as possible logical arrays with optimized networks length. To deal with the faults on switches and links, an efficient pre-processing procedure is designed, in which switch faults are transformed into link faults, and then faulty links are classified into several categories to handle. Then, we propose an efficient algorithm, A-MLA, to produce as many as possible logical columns which are then combined to form a two dimensional processor array. After that, we propose an algorithm A-TMLA to reduce the interconnection length of the logical array obtained by algorithm A-MLA, as short interconnect leads to small communication latency and power consumption. Extensive experimental results show that, even with switch faults and link faults, our approach can produce larger logical fault-free arrays with shorter interconnection length, compared to the state-of-the-art.

关键词： Fault-tolerance processor array switch faults link faults interconnection length

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Optimization of communication cost within processor arrays caused by I/O

Optimization of communication cost within processor arrays c...

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18th IASTED International Conference on Parallel and Distributed Computing and Systems

作者： Siegel, Sebastian Merker, Renate Tech Univ Dresden Inst Circuits & Syst D-01062 Dresden Germany

ISBN: (纸本)9780889866386

Fine grain parallel architectures such as processor arrays (PAs) play an important role in the acceleration of applications which demand high processing capabilities. Methods for the mapping of compute-intensive algorithms to PAs often neglect an efficient routing of input and output (I/O). We formulate an integer linear program (ILP) with the objective to minimize the cost of channels and registers within the PA which are required to route the I/O. This optimization problem is integrated in our framework for the design of PAs. There we use partitioning to map algorithms to PAs. I/O is caused by the algorithm itself and in partitioning by the intermediate data because of the sequential execution of the partitions. The ILP for the routing of the I/O can be combined with an optimization problem which considers the efficient routing of the data dependencies of the algorithm within the PA. We demonstrate the combined approach on the edge detection algorithm.

关键词： processor array input/output interconnection partitioning integer linear programming

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Minimizing interconnect length on reconfigurable meshes

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中国高等学校学术文摘·计算机科学 2009年第3期3卷 315-321页

作者： Jigang WU Thambipillai SRIKANTHAN Kai WANG School of Computer Science and Software Tianjin Polytechnic University Tianjin 300160 China School of Computer Engineering Nanyang Technological University Singapore 639798 Singapore School of Computer Engineering Nanyang Technological University Singapore 639798 Singapore

Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter inter-connect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially gen-erates the middle (|k/2|th) logical column and then makes it nearly straight for the MLA with k logical columns. A dy-namic programming approach is presented to compact other logical columns toward the middle logical column, result-ing in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experi-mental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.

关键词： Mesh reconfiguration processor array routing algorithm

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A comparison between the computational power of PARBS and RMBM

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1996年第5期E79D卷 570-578页

作者： Miyashita, K Tsujino, Y Tokura, N Department of Information and Computer Sciences Osaka University Toyonaka-shi 560 Japan

processor networks connected by buses have attracted considerable attention. Since a reconfigurable array is more powerful than a PRAM and more practical, it becomes the focus of attention. The processor array with Reconfigurable Bus System (PARBS) and the Reconfigurable Multiple Bus Machine (RMBM) are both models of parallel computation based on reconfigurable bus and processor array. The PARBS is a processor array that consists of processors arranged to a 2-dimensional grid with a reconfigurable bus system. The RMBM is also made of processors and reconfigurable bus system, but the processors are located in a row and the number of processors and the number of buses are independent of each other. Four versions of RMBM has been proposed and Extended RMBM (E-RMBM) is regarded as the most powerful one among them. In this paper, we describe that a PARBS of size N x M can be simulated in constant time by a E-RMBM of 4N M processors, M + 3 buses and 1 read buffer, and that a E-RMBM of P processors, B buses and D read buffers can be also simulated in constant time by a PARBS of size B x P. A PARBS or RMBM that solves a computational problem of size n is polynomially bounded iff the product of the number of processors and buses and read and write ports is O(n(c)), for some constant c. When a PARBS is polynomially bounded, the E-RMBM which simulates it is also polynomially bounded, and vice versa.

关键词： parallel computational model processor array reconfigurable bus PARBS RMBM

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SPEED-UP OF SCALABLE ITERATIVE LINEAR SOLVERS IMPLEMENTED ON AN array OF TRANSPUTERS

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PARALLEL COMPUTING 1994年第3期20卷 375-387页

作者： ASENOV, A REID, D BARKER, JR Nanoelectronics Research Centre Department of Electronics and Electrical Engineering The University of Glasgow Glasgow G12 8QQ UK

A detailed model is presented for the speedup of parallel linear iterative solvers. The mapping of a topologically rectangular discrete grid onto a processor array of N x M transputers leads to step-like behaviour in the local communication and calculation time. This results in a typical oscillatory behaviour of 'speedup' when problem sizes are increased monotonously. The theory is compared with experimental results obtained on a Parsytec Super Cluster Model 64 using a black-red SOR algorithm coded in 3L Parallel Fortran.

关键词： PARALLEL ITERATIVE SOLVERS processor array TRANSPUTERS SPEEDUP PREDICTION

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A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting

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IEEE ACCESS 2017年 5卷 23912-23919页

作者： Qian, Junyan Wang, Yiping Chang, Lang Zhou, Zhide Zhao, Lingzhong Guilin Univ Elect Technol Guangxi Key Lab Trusted Software Guilin 541004 Peoples R China

Increasing the size of target arrays is beneficial to reuse fault-free processing elements (PEs) for reconfiguring 2-D mesh-connected processor arrays with faults. In this paper, we discuss the reconfiguration problem under the row and column rerouting constraint. We present a novel approach, making use of the idea of integer programming, for constructing larger size target arrays. Meanwhile, we propose a new method to deal with the fault-free processing elements in the physical row that is selected for exclusion. Compared with the state-of-arts algorithms, our method can make the fault-free PEs used as much as possible, which means the size of the target array can be significantly improved. Experimental results show that, compared with previous studies, the proposed algorithm achieves better results in terms of the usage rate of fault-free PEs in the host array.

关键词： Integer programming fault tolerance reconfiguration processor array algorithm

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Reconfiguration classes and an optimal reconfiguration method within a reconfiguration class

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2002年第12期E85D卷 1909-1917页

作者： Shigei, N Miyajima, H Kagoshima Univ Kagoshima 8900065 Japan

This paper considers a reconfiguration problem on a processor array model based on single-and-half-track switches, which is proposed for a fault tolerance technique at the fabrication time. The focus of this paper is to achieve the optimal reconfigurability, which means that whenever there exists a solution for successful reconfiguration, the designed method can find the solution. The paper consists of two parts. In the first part, we show two essential constraints that have been assumed in most of the previous studies, and make four reconfiguration classes that differ in the assumed essential constraints. Then, we present some inclusion relations among the four reconfiguration classes. As a result, it becomes clear that the most restrictive class including most of the previous methods never achieves the truly optimal reconfigurability. In the second part, we present a reconfiguration method based on sequential routing (RMSR). Although the worst-case time complexity of the RMSR is exponential in the number of processing elements, the reconfigurability of the RMSR is optimal within the most restrictive reconfiguration class. The effectiveness of the RMSR is shown by a computer simulation.

关键词： processor array reconfiguration fault tolerant reconfiguration classes inclusion relation

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Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices

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ALEXANDRIA ENGINEERING JOURNAL 2022年第12期61卷 13079-13087页

作者： Ibrahim, Atef Gebali, Fayez Prince Sattam Bin Abdulaziz Univ Alkharj Coll Comp Engn & Sci Comp Engn Dept Al Kharj Saudi Arabia Univ Victoria ECE Dept Victoria BC Canada

Adoption of IoT technology without considering its security implications may expose network systems to a variety of security breaches. In network systems, IoT edge devices are a major source of security risks. Implementing cryptographic algorithms on most IoT edge devices can be difficult due to their limited resources. As a result, compact implementations of these algorithms on these devices are required. Because the field multiplication operation is at the heart of most cryptographic algorithms, its implementation will have a significant impact on the entire cryptographic algorithm implementation. As a result, in this paper, we propose a small hardware accelerator for performing field multiplication on edge devices. The hardware accelerator is primarily composed of a processor array with a regular structure and local interconnection among its processing elements. The main advantage of the proposed hardware structure is the ability to manage its area, delay, and consumed energy by choosing the appropriate word size l. We implemented the proposed structure using ASIC technology and the obtained results attain average savings in the area of 95.9%. Also, we obtained significant average savings in energy of 63.2%. The acquired results reveal that the offered hardware accelerator is appropriate for usage in resource-constrained IoT edge devices.(c) 2022 THE AUTHORS. Published by Elsevier BV on behalf of Faculty of Engineering, Alexandria University This is an open access article under the CC BY-NC-ND license (http://***/ licenses/by-nc-nd/4.0/).

关键词： Finite field multiplication IoT security Cryptography IoT-edge devices Parallel processing processor array

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