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processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs

MICROprocessorS AND MICROSYSTEMS 2015年第7期39卷 576-588页

作者： Perez-Andrade, Roberto Torres-Huitzil, Cesar Cumplido, Rene CINVESTAV Natl Polytech Inst Ctr Adv Studies Informat Technol Lab Ciudad Victoria Mexico INAOE Natl Inst Astrophys Opt & Elect Dept Comp Sci Santa Maria Tonantzintla Puebla Mexico

Matrix algorithms are an important part of many digital signal processing applications as they are core kernels that are usually required to be applied many times while computing different tasks. Hardware assisted implementations using FPGAs provide a good compromise between performance, cost and power consumption, specially when high level synthesis techniques are employed for deriving co-processors. In this paper a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model is presented. The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as support for solving problems independently of their size and limited only by the FPGA available resources. The proposed approach has been validated by generating processor arrays for three different matrix algorithms used in digital signal processing applications;more precisely matrix-matrix multiplication, Cholesky and LU decomposition algorithms. These algorithms were targeted for a Spartan-6 device and compared against their sequential implementations targeted for a MicroBlaze processor in order to provide a general view of the gain achieved by the processor arrays when the arrays and sequential processors are implemented in the same technology. Results show that the implemented arrays outperforms hardware and software implementations considering an embedded platforms scenario with a Spartan-6 device. (C) 2015 Elsevier B.V. All rights reserved.

关键词： processor arrays Polytope Embedded platforms FPGAs

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DETAILED MODELING AND RELIABILITY-ANALYSIS OF FAULT-TOLERANT processor arrays

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IEEE TRANSACTIONS ON COMPUTERS 1992年第9期41卷 1193-1200页

作者： LOPEZBENITEZ, N FORTES, JAB PURDUE UNIV SCH ELECT ENGNW LAFAYETTEIN 47907

A method for the generation of detailed models of fault-tolerant processor arrays, based on Stochastic Petri Nets (SPN) is presented in this paper. A compact SPN model of the array associates with each transition a set of attributes that includes a discrete probability distribution. Depending on the type of component and the reconfiguration scheme, these probabilities are determined using simulation or closed-form expressions and correspond to the survival of the array given that a number of components required by the reconfiguration process are faulty.

关键词： FAULT-TOLERANCE MARKOV MODELS processor arrays RELIABILITY STOCHASTIC PETRI NETS

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A HYPERGRAPH MODEL FOR FAULT-TOLERANT VLSI processor arrays

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IEEE TRANSACTIONS ON COMPUTERS 1985年第6期34卷 578-584页

作者： ROSENBERG, AL Department of Computer Science Duke University Durham NC 2770 Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

We study here a formal version of a strategy for constructing fault-tolerant VLSI processor arrays in an environment of wafer-scale integration. The strategy achieves tolerance to faults by running buses past the implemented PE"s and interconnecting the fault-free ones into an array of the desired structure by having PE"s tap into the bank of buses. Earlier studies [12] have shown this strategy to be competitive with more familiar strategies, particularly given the availability of laser-welding technology. We study here fault-tolerant implementation of linear arrays and tree-structured arrays, deriving both upper and lower bounds on the area required to lay out the fault-tolerant arrays. We also consider briefly the ❉ of wire lengths.

关键词： Area efficiency buses fault tolerance hypergraphs laser welding linear array of processors processor arrays trees of processors

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AN OPTIMAL DOMAIN-BASED RECONFIGURATION ALGORITHM FOR WSI processor arrays

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1992年第5期33卷 261-278页

作者： KIM, JH RHEE, PK HA, DS UNIV SW LOUISIANA CTR ADV COMP STUDIESLAFAYETTELA 70504 VIRGINIA POLYTECH INST & STATE UNIV BRADLEY DEPT ELECT ENGNBLACKSBURGVA 24061

This paper addresses an optimal reconfiguration algorithm based on the domain constraint. The domain of a logical cell is a set of physical cells where the logical cell can be assigned. It is necessary to justify the correctness of a reconfiguration algorithm through the association of a reconfiguration algorithm to the required channel complexity which satisfies the interconnection requirement of the reconfiguration algorithm. A reconfiguration algorithm is defined as optimal, if it can find a solution with the minimal channel complexity whenever there exists at least one within the predefined constraints. Reconfiguration problem with domain constraint is formalized as complete matching. Since complete matching is a special case of maximal matching, domain-based reconfiguration can be solved by a maximal matching. To obtain the minimal channel complexity, the array is partitioned into as small units as possible while preserving the array reconfigurability. For the six-cell domain, it is proved that 3 x 4 track is the minimal channel complexity. Therefore, our proposed reconfiguration algorithm employing the complete matching and 3 x 4 channel complexity is an optimal reconfiguration algorithm under the constraint of the six-cell domain.

关键词： processor arrays FAULTY CELL DOMAIN RECONFIGURATION

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RECONFIGURING processor arrays USING MULTIPLE-TRACK MODELS - THE 3-TRACK-1-SPARE-APPROACH

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IEEE TRANSACTIONS ON COMPUTERS 1993年第11期42卷 1281-1293页

作者： VARVARIGOU, TA ROYCHOWDHURY, VP KAILATH, T PURDUE UNIV SCH ELECT ENGNW LAFAYETTEIN 47907 STANFORD UNIV INFORMAT SYST LABSTANFORDCA 94305

We present new results on systematic procedures for reconfiguring processor arrays in the presence of faulty processors. In particular, we consider models that use multiple tracks along every channel and a single spare row (or column) of processing elements (PE's) along each boundary of the array. In the presence of faulty PE's the general methodology for reconfiguration involves replacing every faulty PE logically (rather than physically) by a spare PE through a sequence of logical substitutions;these sequences of substitutions are referred to as compensation paths. The determination of such compensation paths for every faulty PE has to be followed by an algorithm to connect each PE to its logical neighbors. It is easy to see that if the number of available routing tracks is fixed, then the compensation paths cannot be arbitrary. Hence, an important question to address is: how many tracks should one provide so as to allow a large enough class of compensation paths, and yet keep the hardware redundancy low. In this paper we show that if there exists a set of compensation paths subjected only to the constraints of continuity and nonintersection, then routing channels with three tracks are enough for the reconfiguration of the array. This theoretical result matches the empirical obseervations presented by several researches showing that three-track routing channels are sufficient for reconfiguring most instances. We refer to the underlying model as a 3-track-1-spare model;this is done to distinguish it from other models that not only use multiple tracks but also multiple spare rows (or columns) along each boundary. We present an efficient algorithm for reconfiguration in our 3-track-1-spare model and evaluate its performance. Our experimental results show that the 3-track-1-spare model has much higher reconfiguration probability than other models that use considerably more spare processors.

关键词： EFFICIENT POLYNOMIAL-TIME RECONFIGURATION ALGORITHMS FAULT-TOLERANT ARCHITECTURE MULTI-TRACK-MODELS processor arrays WSI TECHNOLOGY

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Optimal synthesis of algorithm-specific lower dimensional processor arrays

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1996年第3期7卷 274-287页

作者： Ganapathy, KN Wah, BW UNIV ILLINOIS DEPT ELECT & COMP ENGNURBANAIL 61801 UNIV ILLINOIS COORDINATED SCI LABURBANAIL 61801

processor arrays are frequently used to deliver high performance in many applications with computationally intensive operations. This paper presents the General Parameter Method (GPM), a systematic parameter-based approach for synthesizing such algorithm-specific architectures. GPM can synthesize processor arrays of any lower dimension from a uniform-recurrence description of the algorithm. The design objective is a general nonlinear and nonmonotonic user-specified function, and depends on attributes such as computation time of the recurrence on the processor array, completion time, load time, and drain time. In addition, bounds on some or all of these attributes can be specified. GPM performs an efficient search of polynomial complexity to find the optimal design satisfying the user-specified design constraints. As an illustration, we show how GPM can be used to find optimal linear processor arrays for computing transitive closures. We consider design objectives that minimize computation time, or processor count, or completion time (including load and drain times), and user-specified constraints on number of processing elements and/or computation/completion times. We show that GPM can be used to obtain optimal designs that trade between number of processing elements and completion time, thereby allowing the designer to choose a design that best meets the specified design objectives. We also show the equivalence between the model assumed in GPM and that in the popular dependence-based methods [1], [2]. Consequently, GPM can be used to find optimal designs for both models.

关键词： design constraints objective function optimal design polynomial-time search processor arrays transitive closure uniform recurrence equations

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SYNCHRONIZING LARGE VLSI processor arrays

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IEEE TRANSACTIONS ON COMPUTERS 1985年第8期34卷 734-740页

作者： FISHER, AL KUNG, HT Department of Computer Science Carnegie-Mellon University

Highly parallel VLSI computing structures consist of many processing elements operating simultaneously. In order for such processing elements to communicate among themselves, some provision must be made for synchronization of data transfer. The simplest means of synchronization is the use of a global clock. Unfortunately, large clocked systems can be difficult to implement because of the inevitable problem of clock skews and delays, which can be especially acute in VLSI systems as feature sizes shrink. For the near term, good engineering and technology improvements can be expected to maintain the feasibility of clocking in such systems; however, clock distribution problems crop up in any technology as systems grow. An alternative means of enforcing necessary synchronization is the use of self-timed asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best possible synchronization schemes for large processor arrays are proposed.

关键词： Clock skew VLSI complexity processor arrays synchronization systolic arrays

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REGULAR ITERATIVE ALGORITHMS AND THEIR IMPLEMENTATION ON processor arrays

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PROCEEDINGS OF THE IEEE 1988年第3期76卷 259-269页

作者： RAO, SK KAILATH, T STANFORD UNIV INFORMAT SYST LABSTANFORDCA 94305

Some recent results are summarized concerning a class of algorithms known as regular iterative algorithms, particularly with respect to their implementations on processor arrays. Regular iterative algorithms contain all algorithms executed by systolic arrays as a proper subclass and are therefore of considerable importance in real-time signal processing applications. Some general concepts concerning the design of parallel architectures are introduced, and the importance of devising special techniques that utilize any available structure in the algorithm is highlighted. A generic description of the existing methodologies for the systematic design of systolic arrays is given. Using some simple examples, the limitations of these methods are shown. A formal methodology is proposed that overcomes the difficulties in the existing procedures

关键词： computerised signal processing formal methodology iterative algorithms iterative methods parallel architectures parallel architectures processor arrays real-time signal processing systematic design systolic arrays

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GRACEFULLY DEGRADABLE processor arrays

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IEEE TRANSACTIONS ON COMPUTERS 1985年第11期34卷 1033-1044页

作者： FORTES, JAB RAGHAVENDRA, CS UNIV SO CALIF DEPT ELECT ENGN SYSTLOS ANGELESCA 90089

A new approach to the design of gracefully degradable processor arrays is discussed. Fault tolerance and graceful degradation are achieved by simultaneously reconfiguring the processor array and the algorithm in execution. Two types of algorithm reconfigurability are considered, namely, row reconfigurability (RR) and row-column reconfigurability (RCR). correspondingly, two array reconfiguration schemes are discussed, i.e., successive row elimination (SRE) and alternate row-column elimination (ARCE). It is shown that the computations of any algorithm executable in a processor array can always be (re) organized so that the resultant algorithm has the RR and/or RCR properties. Upper bounds on the increase in execution time of an algorithm due to reorganization of computations for reconfigurability are derived. Detailed analysis of performance and reliability is done for both SRE and ARCE reconfiguration schemes. These reconfiguration techniques are applicable to any processor array and suitable for VLSI technology.

关键词： Algorithm transformations computational availability dynamic reconfiguration graceful degradation performability processor arrays reliability

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RECONFIGURATION STRATEGIES FOR VLSI processor arrays AND TREES USING A MODIFIED DIOGENES APPROACH

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IEEE TRANSACTIONS ON COMPUTERS 1992年第1期41卷 83-96页

作者： BELKHALE, KP BANERJEE, P UNIV ILLINOIS DEPT COMP SCIURBANAIL 61801 UNIV ILLINOIS COORDINATED SCI LABCTR RELIABLE & HIGH PERFORMANCE COMPURBANAIL 61801

Reconfiguration strategies in VLSI processor arrays have been advocated in the recent literature as a means of achieving higher production yield and higher reliability. In this paper, we present new reconfiguration techniques for rectangular arrays and trees that are modifications of the Diogenes approach proposed earlier by Rosenberg et al. These techniques reduce the overheads incurred in the earlier Diogenes schemes. We present two schemes for reconfiguring rectangular arrays and a scheme for reconfiguring trees. For the analysis of the different schemes presented in this paper, we assume that a processor has a square layout. The first scheme for reconfiguring an N x N rectangular array uses tau additional rows and c additional columns. It takes O(tau(N + tau)(N + c) square-root A + (N + tau)(N + c)A) area, where A is the area of a single processor. The scheme guarantees reconfiguration as long there are at most c columns that have more than tau-faulty processors. The second scheme uses S spare processors and O((N2 + S)kappa-square-root A + (N2 + S)A) area. Here kappa is a parameter of the design. It guarantees reconfiguration as long as there are enough spare processors, and in any window of N processors in a particular linearization there are at most kappa-faulty processors. The scheme for reconfiguring a tree can tolerate as many faults as the number of spare processors S. The design uses O((N + S)log(N) square-root A + (N + S)A) area. The link length, even in the case of faults, is O(square-root N(log N + square-root A)).

关键词： ANALYTICAL AND SIMULATION STUDIES CIRCUIT DESIGN LINEARIZATION processor arrays RECONFIGURATION TECHNIQUES TREE TOPOLOGY VLSI LAYOUT

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