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4th International Workshop on Real-Time Computing Systems and Applications (RTCSA 97)

作者： Farber, G Fischer, F Kolloch, T Muth, A Technische Universitaet Muenchen Muenchen Germany

ISBN: (纸本)0818680741

Modern microprocessors with caches and pipelines show increasing performance, but at the price of a decreasing predictability of execution times. The design of hard real-time systems however has to be based on worst case considerations. consequently, real-time systems are generally oversized and fail to profit of developments in the standard processor field. This paper presents an approach where real-time systems are analyzed and built according to a task classification model. Each class of tasks corresponds to a type of processor best suited in terms of performance and deterministic execution times. The resulting target architecture framework is a tightly coupled heterogeneous multiprocessor system based on templates using off-the-shelf components. The described real-time system design process includes a schedulability analysis method that supports the partitioning and allocation process and provides the necessary real-time guarantees. The result is a event-driven hard real-time system with improved processor utilization that will provably meet all its deadlines. A rapid prototyping platform implementing this concept is presented as well as application examples.

关键词： task classification model hard real-time schedulability analysis processor utilization caches

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A Note on the Effect or the Central processor Service Time Distribution on processor utilization in Multiprogrammed Computer Systems

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Journal of the ACM (JACM) 1976年第2期23卷 342-346页

作者： Price, Thomas G. Stanford University Stanford California Collie Roads United States

Upper and lower bounds on processor utilization for the queueing model M/G/1/N are derived. The upper bound is equal to the utilization for constant service times and the lower bound is approached when the average number of operations per busy period approaches one. These bounds show that the form of the processing time distribution can have a substantial effect on processor utilization. We show that the utilization will be near the lower bound if there are a large number of short processing times. The variance does not always give an accurate indication of the effect of the distribution on utilization. © 1976, ACM. All rights reserved.

关键词： multiprogranuning performance evaluation probability models processor utilization queueing theory service time distributions

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Task scheduling through limited duplication with processor utilization in grid computing system

Task scheduling through limited duplication with processor u...

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2nd IEEE International Conference on Parallel, Distributed and Grid Computing (PDGC)

作者： Agarwal, Neha Gupta, Chhavi Khare, Ankit Jaypee Univ Informat Technol Dept CSE & ICT Solan 173234 Himachal Prades India

ISBN: (纸本)9781467329255;9781467329224

In dependent task scheduling algorithms, task duplication is the finest scheduling technique for minimizing the response time of workflow application in grid computing system. When we apply task duplication scheduling algorithm on workflow application, we get shorter schedules (makespan) but it has one limitation that grid node can be overloaded due to duplications of tasks. In this paper we are proposing an algorithm in which we are focusing on three points (1) reducing makespan (2) reducing tasks duplication, and (3) achieving better processor utilization. For this we have suggested an algorithm (TLD-P) which is achieving good results for considered parameters as compared to the existing HLD and EDS-G algorithm.

关键词： Grid Computing Duplication task scheduling processor utilization DAG Workflow applications

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QUEUING THEORETICAL-ANALYSIS OF processor utilization IN PARALLEL COMPUTERS

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COMPUTING SYSTEMS 1993年第1期8卷 13-23页

作者： LAUWEREINS, R PEPERSTRAETE, J KATHOLIEKE UNIV LEUVEN ESAT LABB-3001 HEVERLEEBELGIUM

To analyse the processor utilization of parallel computers, a queueing model is constructed, valid for all computers with point-to-point connections between neighbouring nodes. Using this model, many influences on system performance are presented. As a conclusion, guidelines are offered to both the computer architect and to the application programmer for obtaining the highest possible processor utilization.

关键词： QUEUING THEORY PARALLEL COMPUTERS POINT-TO-POINT INTERCONNECTION NETWORKS DISTRIBUTED MEMORY processor utilization

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utilization-aware Load Balancing for the Energy Efficient Operation of the *** processor 14

Utilization-aware Load Balancing for the Energy Efficient Op...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Myungsun Kim Kibeom Kim James R. Geraci Seongsoo Hong Seoul National University Seoul Korea and DMC R&D Samsung Electronics Suwon Korea DMC R&D Samsung Electronics Suwon Korea Seoul National University Seoul Korea

ISBN: (纸本)9783981537024

ARM's *** architecture introduces the opportunity to optimize power consumption by selecting the core type most suitable for a level of processing demand. To take advantage of this new axis of optimization, we introduce processor utilization into the Linux kernel's load balancing algorithm. Our method improves the Linux kernel's ability to schedule tasks in an energy efficient manner without making it directly aware of the available core types. Experimental results show an energy consumption improvement over the standard Linux scheduler up to 11.35% with almost no reduction in performance.

关键词： Load balancing core type Linux Energy efficiency processor utilization Power consumption processor Seeds Religious Missions

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Multithreaded processors

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COMPUTER JOURNAL 2002年第3期45卷 320-348页

作者： Ungerer, T Robic, B Silc, J Univ Augsburg Dept Comp Sci Augsburg Germany Univ Ljubljana Fac Comp & Informat Sci Ljubljana Slovenia Jozef Stefan Inst Comp Syst Dept Ljubljana Slovenia

The instruction-level parallelism found in a conventional instruction stream is limited. Studies have shown the limits of processor utilization even for today's superscalar microprocessors. One solution is the additional utilization of more coarse-grained parallelism. The main approaches are the (single) chip multiprocessor and the multithreaded processor which optimize the throughput of multiprogramming workloads rather than single-thread performance. The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip. In contrast, the multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline. Unused instruction slots, which arise from pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor. The execution units are multiplexed between the threads in the register sets. Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple threads each cycle. Simultaneous multithreaded processors combine the multithreading technique with a wide-issue superscalar processor such that the full issue bandwidth is utilized by potentially issuing instructions from different threads simultaneously. This survey paper explains and classifies the various multithreading techniques in research and in commercial microprocessors and compares multithreaded processors with chip multiprocessors.

关键词： processor utilization processor Multithreading macroprocessor superscalar processor Multiprocessor instruction-level parallelism instruction Computer chips

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Analysis of parallel processing effects through a co-processor in diesel engine management system

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INTERNATIONAL JOURNAL OF AUTOMOTIVE TECHNOLOGY 2015年第5期16卷 813-820页

作者： Sohn, J. Hong, S. Park, I. Kwon, J. Lee, W. Sunwoo, M. Hanyang Univ Grad Sch Dept Automot Engn Seoul 133791 South Korea Hanyang Univ Automot Control & Elect Lab Seoul 133791 South Korea Changwon Natl Univ Dept Control & Instrumentat Engn Gyeongnam 641773 South Korea Hanyang Univ Dept Automot Engn Seoul 133791 South Korea

We show that computational load can be reduced when a programmable co-processor is used for a time-critical system design. We analyze the real-time performances of a diesel engine management system by applying a programmable timer co-processor. In order to verify the performances caused by the co-processor, we investigated the timing parameters such as the process time, execution period, and processor utilization, according to a changing task structure. The processor utilizations of the tasks were found to be reduced within the range of 0.65% to 33.68% on worst-case execution period condition. These results show that an appropriate task construction considering the co-processor characteristics can lead to improvement in real-time performance from parallel processing on par with a multicore processor system even under limited conditions.

关键词： Co-processor Diesel engine Engine management system Fuel injection system processor utilization Time processor unit

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SPOKEN LANGUAGE RECOGNITION ON A DSP ARRAY processor

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1994年第7期5卷 697-703页

作者： GLINSKI, S ROE, D AT and T Bell Laboratories Inc. Murray Hill NJ USA

A new architecture is presented to support the general class of real-time large-vocabulary speaker-independent continuous speech recognizers incorporating language models. Many such recognizers require multiple high-performance central processing units (CPU's) as well as high interprocessor communication bandwidth. This array processor provides a peak CPU performance of 2.56 giga-floating point operations per second (GFLOPS) as well as a high-speed communication network. In order to efficiently utilize these resources, algorithms were devised for partitioning speech models for mapping into the array processor. Also, a novel scheme is presented for a functional partitioning of the speech recognizer computations. The recognizer is functionally partitioned into six stages, namely, the linear predictive coding (LPC) based feature extractor, mixture probability computer, (phone) state probability computer, word probability computer, phrase probability computer, and traceback computer. Each of these stages is further subdivided as many times as necessary to fit the individual processing elements (PE's). The functional stages are pipelined and synchronized with the frame rate of the incoming speech signal. This partitioning also allows a multistage stack decoder to be implemented for reduction of computation. The fully configured array processor is composed of 128 PE's, each of which comprises a floating point digital signal processor, a local memory of 64-kilobyte by 32-bit words, and a custom communications device that permits each PE to talk with four adjacent PE's in a 2-D grid. A second communication network provides global communication between a host processor and each PE. Each node is programmable in the high-level C language. One recognizer we have implemented at AT&T uses 1759 phonelike units (PLU's). These units comprise phones, di hones, and triphones that are selected based on their frequency of occurrence in the training corpus. Each PLU is modeled with a thr

关键词： ARRAY processor DIGITAL SIGNAL processorS FUNCTIONAL DECOMPOSITION GRAMMAR PARTITION MESSAGE-PASSING ARCHITECTURE processor utilization SPEECH RECOGNITION

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Incorporating temporal considerations during assignment and pre-run-time scheduling of objects and processes

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 1996年第1期36卷 13-31页

作者： Verhoosel, JPC Welch, LR Hammer, DK Luit, EJ NEW JERSEY INST TECHNOL DEPT COMP & INFORMAT SCINEWARKNJ 07102 EINDHOVEN UNIV TECHNOL DEPT MATH & COMP SCINL-5600 MB EINDHOVENNETHERLANDS

Object-based programming techniques help to reduce the cost of software development and maintenance due to the benefits of reuse, information hiding, and encapsulation. This is especially helpful in large, real-time systems that are highly parallel and distributed. The paper reviews a semi-preemption execution model of object-based real-time systems that simplifies reasoning about the quality of process-to-processor assignment. The model is used to define system properties such as interprocess parallelism, processor utilization, and interprocessor communication. Additionally, an innovative assignment algorithm is presented which incorporates feasibility constraints. The algorithm is guided by an objective that balances minimum communication against maximum parallelism. Experimental results show that the process assignment algorithm performs extremely well with respect to finding process assignments in isolation. The algorithm easily finds process assignments for which a feasible schedule exists as long as the number of items to be scheduled does not exceed approximately 500. (C) 1996 Academic Press, Inc.

关键词： Programs System computer software Synclitism processor utilization parallelism interprocessor communication real-time systems object orientation Reasoning encapsulation Allocation Algorithm

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Energy-efficient scheduling with reliability guarantee in embedded real-time systems

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SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS 2018年 18卷 137-148页

作者： Xu, Hongzhi Li, Renfa Zeng, Lining Li, Keqin Pan, Chen Hunan Univ Coll Informat Sci & Engn Changsha 410082 Hunan Peoples R China Jishou Univ Coll Software & Serv Outsourcing Zhangjiajie 427000 Peoples R China SUNY Coll New Paltz Dept Comp Sci New Paltz NY 12561 USA Oklahoma State Univ Sch Elect & Comp Engn Stillwater OK 74078 USA

Embedded systems have been widely applied in many areas such as aerospace, intelligent transportation, smart grid, and, medical care. However, limited energy supply and runtime faults are two challenges that hinder the embedded system to be even more pervasively applied. In this paper a greedy energy-efficient (GEE) algorithm is proposed to improve the energy efficiency under the constraint of reliability. As GEE may lead to more preemptions with reduced execution frequency, this paper analyzes the preemption during the execution and proposes a series of constraints to reduce the frequency of preemption. This reduces both the energy consumption and execution time. To further balance the execution frequency, two energy-efficient algorithms are presented based the processor utilization. Finally, considering the fact that the actual execution time (AET) of many tasks may be less than the worst-case execution time (WCET), a global dynamic scheduling algorithm is proposed to maximize the energy efficiency while ensuring the reliability. The experimental results show that the proposed techniques have significant improvements of energy efficiency with guaranteed system reliability. (C) 2018 Elsevier Inc. All rights reserved.

关键词： Energy efficiency processor utilization Real-time system Reliability Task scheduling

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