Different characteristics of algorithms, perform better or worse on various target hardware. The consequent of this is, that the selection of one suitable hardware, such as Graphic Processing Units (GPU), Field Progra...
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ISBN:
(纸本)9781457704345
Different characteristics of algorithms, perform better or worse on various target hardware. The consequent of this is, that the selection of one suitable hardware, such as Graphic Processing Units (GPU), Field Programmable Gate Arrays (FPGAs) or traditional processor cores is a challenging task for developers. The challenge is to choose the most suitable platform satisfying the requirements of the given application, such as real-time and power- / energy consumption constraints. Due to short time to market pressure, a fast development cycle is also a very important characteristic in industrial applications. This work evaluates the performance, power- / energy consumption and the development effort for three processor-based systems: an FPGA-based multiprocessor platform called RAMPSoC, a GPU and a CPU. Two real-world applications have been selected for this evaluation: 3D Ultrasound Computer Tomography and Object Recognition. The paper presents the realization of the applications on the different target hardware and discusses the results of the power and performance evaluation.
In microprocessor- basedsystems, evaluating the criticality of registers is required in order to achieve the expected dependability level with respect to soft errors and to guide selective improvements for a given ap...
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ISBN:
(纸本)9781509020768
In microprocessor- basedsystems, evaluating the criticality of registers is required in order to achieve the expected dependability level with respect to soft errors and to guide selective improvements for a given application program. Methods have been proposed to perform such criticality evaluations at compile time. Several criteria can be used. We analyze in this paper the impact of compilation optimizations on the system dependability, taking into account the main criteria. We show that specific optimizations are required when dependability is more important than performance or size.
Hardening processor-based systems against transient faults requires new techniques able to combine high fault detection capabilities with the usual design requirements, e.g., reduced design-time, low area overhead, re...
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Hardening processor-based systems against transient faults requires new techniques able to combine high fault detection capabilities with the usual design requirements, e.g., reduced design-time, low area overhead, reduced (or null) accessibility to processor internal hardware. This paper proposes the adoption of a hybrid approach, which combines ideas from previous techniques based on software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads, to harden systembased on the PowerPC 405 core available in Virtex-II Pro FPGAs. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results including comparisons with previous approaches are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory and performance overheads.
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