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A Low-Power Analog processor-in-memory-Based Convolutional Neural Network for Biosensor Applications

SENSORS 2022年第12期22卷 4555-4555页

作者： Byun, Sung-June Kim, Dong-Gyun Park, Kyung-Do Choi, Yeun-Jin Kumar, Pervesh Ali, Imran Kim, Dong-Gyu Yoo, June-Mo Huh, Hyung-Ki Jung, Yeon-Jae Kim, Seok-Kee Pu, Young-Gun Lee, Kang-Yoon Sungkyunkwan Univ Dept Elect & Comp Engn Suwon 16419 South Korea SKAIChips Suwon 16419 South Korea Sungkyunkwan Univ Dept Artificial Intelligence Suwon 16419 South Korea

This paper presents an on-chip implementation of an analog processor-in-memory (PIM)-based convolutional neural network (CNN) in a biosensor. The operator was designed with low power to implement CNN as an on-chip device on the biosensor, which consists of plates of 32 x 32 material. In this paper, 10T SRAM-based analog PIM, which performs multiple and average (MAV) operations with multiplication and accumulation (MAC), is used as a filter to implement CNN at low power. PIM proceeds with MAV operations, with feature extraction as a filter, using an analog method. To prepare the input feature, an input matrix is formed by scanning a 32 x 32 biosensor based on a digital controller operating at 32 MHz frequency. memory reuse techniques were applied to the analog SRAM filter, which is the core of low power implementation, and in order to accurately grasp the MAC operational efficiency and classification, we modeled and trained numerous input features based on biosignal data, confirming the classification. When the learned weight data was input, 19 mW of power was consumed during analog-based MAC operation. The implementation showed an energy efficiency of 5.38 TOPS/W and was differentiated through the implementation of 8 bits of high resolution in the 180 nm CMOS process.

关键词： convolutional neural network processor-in-memory AI controller smart sensing controller on-chip implementation on a biosensor

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NASA Technical Reports Server (Ntrs) 20100014088: Programs for Testing processor-in-memory Computing Systems

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2017年

NASA Technical Reports Server (Ntrs) 20100014088: Programs for Testing processor-in-memory Computing Systems by NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20100014088: computer programs computing katz, daniel s. memory (computers) nasa technical reports server (ntrs) processor-in-memory programs simulators test facilities tradeoffs unix (operating system)

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SE-PIM: In-memory Acceleration of Data-Intensive Confidential Computing

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IEEE TRANSACTIONS ON CLOUD COMPUTING 2023年第3期11卷 2473-2490页

作者： Duy, Kha Dinh Lee, Hojoon Sungkyunkwan Univ Dept Comp Sci & Engn Seoul 03063 South Korea

Demand for data-intensive workloads and confidential computing are the prominent research directions shaping the future of cloud computing. Computer architectures are evolving to accommodate the computing of large data. Meanwhile, a plethora of works has explored protecting the confidentiality of the in-cloud computation in the context of hardware-based secure enclaves. However, the approach has faced challenges in achieving efficient large data computation. In this article, we present a novel design, called se-pim, that retrofits Processing-In-memory (PIM) as a data-intensive confidential computing accelerator. PIM-accelerated computation renders large data computation highly efficient by minimizing data movement. Based on our observation that moving computation closer to memory can achieve efficiency of computation and confidentiality of the processed information simultaneously, we study the advantages of confidential computing inside memory. We construct our findings into a software-hardware co-design called se-pim. Our design illustrates the advantages of PIM-based confidential computing acceleration. We study the challenges in adapting PIM in confidential computing and propose a set of imperative changes, as well as a programming model that can utilize them. Our evaluation shows se-pim can provide a side-channel resistant secure computation offloading and run data-intensive applications with negligible performance overhead compared to the baseline PIM model.

关键词： Cloud computing Computer architecture memory management Computational modeling Hardware Random access memory Computational efficiency processor-in-memory confidential computing

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An Overlay Architecture for Pattern Matching 30

An Overlay Architecture for Pattern Matching

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30th IEEE International Conference on Application-Specific Systems, Architectures and processors (ASAP)

作者： Karakchi, Rasha Daniels, Charles Bakos, Jason Univ South Carolina Columbia SC 29208 USA

ISBN: (纸本)9781728116013

Deterministic and Non-deterministic Finite Automata (DFA and NFA) comprise the fundamental unit of work for many emerging bigdata applications, motivating recent efforts to develop Domain-Specific architectures (DSAs) to exploit fine-grain parallelism available in automata workloads. In this paper we present NAPOLY (Non-Deterministic Automata processor OverLaY), an overlay architecture and associated software that attempts to maximally exploit on-chip memory parallelism for NFA evaluation. In order to avoid an upper bound on NFA size that commonly affects prior efforts, NAPOLY is optimized for runtime reconfiguration, allowing for full reconfiguration in 10s of microseconds. NAPOLY is also parameterizable, allowing for offline generation of a repertoire of overlay configurations with various trade-offs between state capacity and transition capacity. In this paper we evaluate NAPOLY using our proposed state mapping heuristic and the ANMLZoo benchmark suite, and we compare NAPOLY's performance against existing CPU and GPU implementations. To the best of the authors' knowledge this is the first example of a runtime-reprogrammable FPGA-based automata processor overlay.

关键词： overlay automata processor NFA DFA processor-in-memory reconfigurable computing pattern matching heterogeneous computing domain-specific processor DSL DSA big data data analytics data processing text processing deep-packet inspection state machine

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StaleLearn: Learning Acceleration with Asynchronous Synchronization Between Model Replicas on PIM

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IEEE TRANSACTIONS ON COMPUTERS 2018年第6期67卷 861-873页

作者： Lee, Joo Hwan Kim, Hyesoon Samsung Semicond Inc San Jose CA 95134 USA Georgia Inst Technol Sch Comp Sci Atlanta GA 30332 USA

GPU has become popular with a large amount of parallelism found in learning. While the GPU has been effective for many learning tasks, still many GPU learning applications have low execution efficiency due to sparse data. Sparse data induces divergent memory accesses with low locality, thereby consuming a large fraction of execution time transferring data across the memory hierarchy. Although a considerable effort has been devoted to reducing the memory divergence, iterative-convergent learning provides a unique opportunity to achieve full potential in modern GPUs that it allows different threads to continue computation using stale values. In this paper, we propose StaleLearn, a learning acceleration mechanism to reduce the memory divergence overhead of GPU learning by utilizing the stale value tolerance of the iterative-convergent learning. Based on the stale value tolerance, StaleLearn transforms the problem of divergent memory accesses into the synchronization problem by replicating the model and reduces the synchronization overhead by asynchronous synchronization on processor-in-memory (PIM). The stale value tolerance enables a clear task decomposition between the GPU and PIM, which can effectively exploit parallelism between PIM and GPU. On average, our approach accelerates representative GPU learning applications by 3.17 times with existing PIM proposals.

关键词： Learning acceleration asynchronous synchronization GPU memory divergence stale value tolerance problem transformation processor-in-memory

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The Superstrider Architecture: Integrating Logic and memory towards non-von Neumann Computing

The Superstrider Architecture: Integrating Logic and Memory ...

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IEEE International Conference on Rebooting Computing (ICRC)

作者： Srikanth, Sriseshan Conte, Thomas M. DeBenedictis, Erik P. Cook, Jeanine Georgia Inst Technol Atlanta GA 30332 USA Sandia Natl Labs Ctr Res Comp POB 5800 Albuquerque NM 87185 USA

ISBN: (纸本)9781538615539

We present a new non-von Neumann architecture, termed "Superstrider," predicated on no more than current projected improvements in semiconductor components and 3D manufacturing technologies, which should offer orders of magnitude advances in both energy efficiency and performance for many high-utility problem classes. The architecture is described, which is based on computing on row-wide memory words to accelerate sparse matrix algebraic operations that are normally implemented as scalar operations. A cycle-accurate simulation demonstrates potential performance improvements on existing High Bandwidth memory (HBM) on the order of 50x that increases to 1000x or more when implemented using a fully integrated 3D technology and compared to a simple baseline. Further refinement may change these numbers, but the magnitude of the opportunity suggests further work.

关键词： Moore's law superstrider processor-in-memory component von Neumann sparse matrix associative array

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Superstrider Associative Array Architecture Approved for unlimited unclassified release SAND2017-7089 C

Superstrider Associative Array Architecture Approved for unl...

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IEEE High Performance Extreme Computing Conference (HPEC)

作者： DeBenedictis, Erik P. Cook, Jeanine Srikanth, Sriseshan Conte, Thomas M. Sandia Natl Labs Ctr Res Comp POB 5800 M-S 1319 Albuquerque NM 87185 USA Georgia Inst Technol Sch Comp Sci Atlanta GA 30332 USA

ISBN: (纸本)9781538634721

We define the Superstrider architecture and report simulation results that show it could be key to achieving HIVE hardware goals. Superstrider's performance comes from a novel sparse-to-dense stream converter, which relies on 3D manufacturing to tightly couple DRAM to an internal network so operations like merging and parallel prefix can be performed quickly and efficiently. With the ability to use the stream converter as a programming primitive, the memory-bound low-level graph operations that we are aware of speed up substantially. We give special attention to triangle counting in this paper. Simulations detailed elsewhere' show 50-1,000x improvement in speed and energy efficiency. The low end of the range should be achievable by constructing a custom controller for current High Bandwidth memory (HBM) where the high end would require fully integrated 3D that is on roadmaps for the future.

关键词： Superstrider Moore's law 3D chips sorting processor-in-memory sparse matrix backpropagation associative array GraphChallenge

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An efficient data-distribution mechanism in a processor-in-memory (PIM) architecture applied to motion estimation

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IEEE TRANSACTIONS ON COMPUTERS 2008年第3期57卷 375-388页

作者： Kang, Jung-Yup Gupta, Sandeep Gaudiot, Jean-Luc Mindspeed Technol Inc Lib & IP Grp Newport Beach CA 92660 USA Univ So Calif Dept Elect Engn Syst Los Angeles CA 90089 USA Univ Calif Irvine Dept Elect & Comp Sci Henry Samueli Sch Engn Irvine CA 92697 USA

In general, the main purpose of using processor-in-memory (PIM) modules is to dramatically increase the Data-Level Parallelism (DLP) and avoid the limited issue rate of current systems (even when they include SIMD extensions) caused by the limited data bandwidth and functional units. Our approach is to divide the PIM module into hundreds of smaller pieces so that each of these smaller PIMs can execute motion estimation for a group of macro blocks in a parallel fashion. We also design the logic in each PIM to execute in a highly pipelined fashion so that even more parallelism can be exploited. The main contribution of this paper is the presentation of architectural techniques that can be used in the PIM module to overcome the addressing and data sharing overhead when these smaller PIMs are used. Our architectural techniques have been applied to motion estimation. Indeed, it has been reported that motion estimation takes the majority of the execution time of MPEG encoding and it has been researched by many because of its importance in MPEG encoding. With our paradigm and techniques, the host processor can be relieved from the most computationally demanding and data-intensive portions of the workload, which should therefore yield a significant performance gain. Indeed, we observed (when 512 of these smaller PIMs were used) a reduction in the number of memory accesses by a factor of up to 2,034 times. At the same time, the performance improved by a multiplicative factor as high as 439 times.

关键词： PIM processor-in-memory motion estimation

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A multi-streaming SIMD multimedia computing engine

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MICROprocessorS AND MICROSYSTEMS 2010年第7-8期34卷 247-258页

作者： Chiu, Jih-Ching Chou, Yu-Liang Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung 804 Taiwan

Current multimedia extensions provide a mechanism for general-purpose processors to meet the growing performance demand of multimedia applications. However, the computing performance of these extensions is often limited for the design conceptions of the single data stream. This paper presents an architecture called "multi-streaming SIMD" that enables current multimedia extensions to simultaneously manipulate multiple data streams. To efficiently and flexibly realize the proposed architecture, an operation cell is designed by fusing the logic gates and the storage cells together. Multiple operation cells then are connected to compose a register file with the ability of performing SIMD operations called "Multimedia Operation Storage Unit (MOSU)". Further, many MOSUs are used to compose a multi-streaming SIMD computing engine that can simultaneously manipulate multiple data streams and exploit the subword parallelisms of the elements in each data stream. This paper also designs three instruction modes (global, coupling, and isolated modes) for programmers to dynamically configure the multi-streaming SIMD computing engine at the instruction level to manipulate different amounts of data streams. Simulation results show that when the multi-streaming SIMD architecture has four 4-register MOSUs, it provides a factor of 3.3x-5.5x performance enhancement for traditional MMX extensions on 12 multimedia kernels. (C) 2010 Elsevier B.V. All rights reserved.

关键词： SIMD Multimedia processing PIM processor-in-memory Multimedia extensions MMX

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memory-side prefetching for linked data structures for processor-in-memory systems

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2005年第4期65卷 448-463页

作者： Hughes, CJ Adve, SV Intel Corp Architecture Res Lab Santa Clara CA 94054 USA Univ Illinois Dept Comp Sci Urbana IL 61801 USA

This paper studies a memory-side prefetching technique to hide latency incurred by inherently serial accesses to linked data structures (LDS). A programmable engine sits close to memory and traverses LDS independently from the processor. The engine can run ahead of the processor because of its low latency path to memory, allowing it to initiate data transfers earlier than the processor and pipeline multiple transfers over the network. We evaluate the proposed memory-side prefetching scheme for the Olden benchmarks on a processor-in-memory system. For the six benchmarks where LDS memory stall time is significant, the memory-side scheme reduces execution time by an average of 27% compared to a system without any prefetching. Compared to a state-of-the-art processor-side software prefetching scheme, the memory-side scheme reduces execution time in the range of 20-50% for three of the six applications, is about the same for two applications, and is worse by 18% for one application. We conclude that our memory-side scheme is effective, but a combination of the processor- and memory-side prefetching schemes is best and provide a qualitative framework to determine when either scheme should be used. (c) 2004 Elsevier Inc. All rights reserved.

关键词： prefetching processor-in-memory linked data structures

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