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Bounded verification for finite-field-blasting in a compiler for zero knowledge proofs

Formal Methods in System Design 2025年 1-28页

作者： Ozdemir, Alex Wahby, Riad S. Brown, Fraser Barrett, Clark Stanford Stanford United States Carnegie Mellon Pittsburgh United States

Zero Knowledge Proofs (ZKPs) are cryptographic protocols by which a prover convinces a verifier of the truth of a statement without revealing any other information. Typically, statements are expressed in a high-level language and then compiled to a low-level representation on which the ZKP operates. Thus, a bug in a ZKP compiler can compromise the statement that the ZK proof is supposed to establish. This paper takes a step towards ZKP compiler correctness by partially verifying a field-blasting compiler pass, a pass that translates Boolean and bit-vector logic into equivalent operations in a finite field. First, we define correctness for field-blasters and ZKP compilers more generally. Next, we describe the specific field-blaster using a set of encoding rules and define verification conditions for individual rules. Finally, we connect the rules and the correctness definition by showing that if our verification conditions hold, the field-blaster is correct. We have implemented our approach in the CirC ZKP compiler and have proved bounded versions of the corresponding verification conditions using an SMT solver. We show that our partially verified field-blaster does not hurt the performance of the compiler or its output;we also report on four bugs uncovered during verification. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.

关键词： program compilers

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Faster Chaitin-like Register Allocation via Grammatical Decompositions of Control-Flow Graphs 25

Faster Chaitin-like Register Allocation via Grammatical Deco...

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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Cai, Xuran Goharshady, Amir Kafshdar Hitarth, S. Lam, Chun Kit Hong Kong University of Science and Technology Clear Water Bay New Territories Hong Kong University of Oxford Oxford United Kingdom

ISBN: (纸本)9798400706981

It is well-known that control-flow graphs (CFGs) of structured programs are sparse. This sparsity has been previously formalized in terms of graph parameters such as treewidth and pathwidth and used to design faster parameterized algorithms for numerous compiler optimization, model checking and program analysis tasks. In this work, we observe that the known graph sparsity parameters fail to exactly capture the kind of sparsity exhibited by CFGs. For example, while all structured CFGs have a treewidth of at most 7, not every graph with a treewidth of 7 or less is realizable as a CFG. As a result, current parameterized algorithms are solving the underlying graph problems over a more general family of graphs than the CFGs. To address this problem, we design a new but natural concept of graph decomposition based on a grammar that precisely captures the set of graphs that can be realized as CFGs of programs. We show that our notion of decomposition enables the same type of dynamic programming algorithms that are often used in treewidth/pathwidth-based methods. As two concrete applications, using our grammatical decomposition of CFGs, we provide asymptotically more efficient algorithms for two variants of the classical problem of register allocation as defined by Chaitin, i.e. assigning program variables to a limited number of registers such that variables with intersecting lifetimes are not assigned to the same register. Note that Chaitin's formulation of register allocation does not allow live-range splitting. Our algorithms are asymptotically faster not only in comparison with the non-parameterized solutions for these problems, but also compared to the state-of-the-art treewidth/pathwidth-based approaches in the literature. For minimum-cost register allocation over a fixed number of registers, we provide an algorithm with a runtime of O(|G| ·|V|5.r) where |G| is the size of the program, is the set of program variables and r is the number of registers. In contrast, the

关键词： program compilers

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Constructing Trustworthy Smart Contracts 26th

Constructing Trustworthy Smart Contracts

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26th International Conference on Verification Model Checking and Abstract Interpretation

作者： Chait-Roth, Devora Namjoshi, Kedar S. NYU New York NY USA Nokia Bell Labs Murray Hill NJ 07974 USA

ISBN: (纸本)9783031827020;9783031827037

Smart contracts form the core of Web3 applications. Contracts mediate the transfer of cryptocurrency, making them irresistible targets for hackers. We introduce Asp, a system aimed at easing the construction of provably secure contracts. The Asp system consists of three closely-linked components: a programming language, a defensive compiler, and a proof checker. The language semantics guarantee that Asp contracts are free of commonly exploited vulnerabilities such as arithmetic overflow and reentrancy. The defensive compiler enforces the semantics and translates Asp to Solidity, the most popular contract language. Deductive proofs establish functional correctness and freedom from critical vulnerabilities such as unauthorized access.

关键词： program compilers

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Towards Studying the Effect of Compiler Optimizations and Software Randomization on GPU Reliability 16

Towards Studying the Effect of Compiler Optimizations and So...

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16th Workshop on Parallel programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025

作者： López Castillón, Pau Hernández, Xavier Caricchio Kosmidis, Leonidas Spain Spain

ISBN: (纸本)9783959773638

The evolution of Graphics Processing Unit (GPU) compilers has facilitated the support for generalpurpose programming languages across various architectures. The NVIDIA CUDA Compiler (NVCC) employs multiple compilation levels prior to generating machine code, implementing intricate optimizations to enhance performance. These optimizations influence the manner in which software is mapped to the underlying hardware, which can also impact GPU reliability. TASA is a source-to-source code randomization tool designed to alter the mapping of software onto the underlying hardware. It achieves this by generating random permutations of variable and function declarations, thereby introducing random padding between declarations of different types and modifying the program memory layout. Since this modifies their location in the memory, it also modifies their cache placement, affecting both their execution time (due to the different conflicts between them, which result in a different amount of cache misses in every execution), as well as their lifetime in the cache. In this work, which is part of the HiPEAC Student Challenge 2025, we first examine the reproducibility of a subset of data presented in the ACM TACO paper "Assessing the Impact of Compiler Optimizations on GPU Reliability"[10], and second we extend it by combining it with our proposal of software randomization. The paper indicates that the -O3 optimization flag facilitates an increased workload before failures occur within the application. By employing TASA, we investigate the impact of GPU randomization on reliability and performance metrics. By reproducing the results of the paper on a different GPU platform, we observe the same trend as reported in the original publication. Moreover, our preliminary results with the application of software randomization show in several cases an improved Mean Waiting Before Failure (MWBF) compared to the original source code. © Pau López Castillón, Xavier Caricchio Hernández, and Le

关键词： program compilers

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LLAMA-2 Acceleration Using the ARM Scalable Vector Extension

LLAMA-2 Acceleration Using the ARM Scalable Vector Extensio...

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International Conference on Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES 2024

作者： Rossi, Federico Cococcioni, Marco Saponara, Sergio Department of Information Engineering University of Pisa Via G. Caruso 16 PI Pisa Italy

ISBN: (纸本)9783031840999

The rise of large language models (LLMs) has spurred recent advances in artificial intelligence (AI), transforming natural language generation and processing. These models perform exceptionally well in a variety of tasks, including machine translation and sentiment analysis, thanks to their unparalleled size and complexity. However, their complexity poses computational difficulties that call for strong hardware acceleration and effective algorithms. To tackle this, we investigate how to speed up LLM processes using the ARM Scalable Vector Extension (SVE). With its ability to vectorize, SVE can potentially improve ARM-based processors’ parallel processing. We present the results of this approach, describing the features of SVE, and going over optimization strategies for LLMs on high-performance computing systems. The results of our experiments show how SVE auto-vectorization enables a speed-up by a factor of up to 4.25× in training time compared to a non-SVE optimized code. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： program compilers

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CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels 31

CROSS: Compiler-Driven Optimization of Sparse DNNs Using Spa...

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31st IEEE International Symposium on High Performance Computer Architecture, HPCA 2025

作者： Liu, Fangxin Huang, Shiyuan Yang, Ning Wang, Zongwu Li, Haomin Jiang, Li Shanghai Jiao Tong University Department of Computer Science and Engineering China Shanghai Qi Zhi Institute China

ISBN: (纸本)9798331506476

As deep learning models continue to grow larger and more complex, exploiting sparsity is becoming one of the most critical areas for enhancing efficiency and scalability. Several methods for leveraging sparsity have been proposed to more effectively balance the trade-off between compression ratio and accuracy. While these methods offer algorithmic advantages, they also introduce significant hardware overhead due to index-based encoding and decoding. In this paper, we propose CROSS, an end-to-end compilation optimization technique to achieve sparse DNN acceleration using GPU computation kernels. The key insight behind CROSS is to exploit parameter distribution locality and reconcile the 'sparse' DNN computation with the high-performance 'dense' computation kernels. Specifically, we perform an in-depth analysis of sparse operations in mainstream DNN computing frameworks. We then decompose the sparse workload into multiple components to create highly efficient, specialized operators with different sparsity levels. Additionally, we introduce a novel sparse graph translation technique to facilitate computation kernel processing of the sparse workload. The resulting CROSS framework can accommodate various sparsity patterns and optimization techniques, delivering an average 2.03 × speedup on inference latency compared to seven state-of-the-art solutions with smaller memory footprints across various models and datasets. © 2025 IEEE.

关键词： program compilers

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FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis 25

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-...

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33rd ACM/SIGDA International Symposium on Field-programmable Gate Arrays, FPGA 2025

作者： Coulon, Louis Ramirez, Lucas Anderson, Jason Stojilović, Mirjana Ienne, Paolo School of Computer and Communication Sciences EPFL Lausanne Switzerland Electrical and Computer Engineering Department University of Toronto Toronto Canada

ISBN: (纸本)9798400713965

Reconfigurable computing fabrics include FPGAs and CGRAs. FPGAs offer flexible bit-level reconfigurability and can map almost any program via high-level synthesis (HLS) compilers, but they incur high area and speed overheads compared to ASICs. CGRAs, in contrast, provide ASIC-like performance but limited flexibility, typically supporting only feedforward programs with unambiguous memory accesses, far from the capabilities of HLS compilers. This work introduces a new class of reconfigurable arrays inspired by modern dynamically scheduled HLS (DHLS) tools. Unlike traditional HLS, DHLS compilers no longer produce explicit state machines, eliminating the need for look-up tables. Instead, they delegate scheduling decisions to a set of coarse-grained primitives. Our arrays leverage these primitives as processing elements and combine FPGA-style interconnect topology for high routing flexibility with CGRA-like bus-based interconnect. We present a framework to explore these arrays and evaluate a preliminary architecture using DHLS benchmarks. The results show an average of ∼2× speed improvement, but unfortunately only a ∼20% area reduction compared to an FPGA implemented on the same technology node. © 2025 Copyright held by the owner/author(s).

关键词： program compilers

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The MLIR Transform Dialect Your Compiler Is More Powerful Than You Think 25

The MLIR Transform Dialect Your Compiler Is More Powerful Th...

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23rd ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2025

作者： Lücke, Martin Paul Zinenko, Oleksandr Moses, William S. Steuwer, Michel Cohen, Albert University of Edinburgh Edinburgh United Kingdom Google DeepMind Paris France University of Illinois Urbana-ChampaignIL United States Google DeepMind CambridgeMA United States Technische Universität Berlin Berlin Germany

ISBN: (纸本)9798400712753

To take full advantage of a specific hardware target, performance engineers need to gain control on compilers in order to leverage their domain knowledge about the program and hardware. Yet, modern compilers are poorly controlled, usually by configuring a sequence of coarse-grained monolithic black-box passes, or by means of predefined compiler annotations/pragmas. These can be effective, but often do not let users precisely optimize their varying compute loads. As a consequence, performance engineers have to resort to implementing custom passes for a specific optimization heuristic, requiring compiler engineering expert knowledge. In this paper, we present a technique that provides fine-grained control of general-purpose compilers by introducing the Transform dialect, a controllable IR-based transformation system implemented in MLIR. The Transform dialect empowers performance engineers to optimize their various compute loads by composing and reusing existing—but currently hidden—compiler features without the need to implement new passes or even rebuilding the compiler. We demonstrate in five case studies that the Transform dialect enables precise, safe composition of compiler transformations and allows for straightforward integration with state-of-the-art search methods. © 2025 Copyright held by the owner/author(s).

关键词： program compilers

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Empowering WebAssembly with Thin Kernel Interfaces 25

Empowering WebAssembly with Thin Kernel Interfaces

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20th European Conference on Computer Systems, EuroSys 2025, co-located 30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Ramesh, Arjun Huang, Tianshu Titzer, Ben L. Rowe, Anthony Carnegie Mellon University PittsburghPA United States Carnegie Mellon University Bosch Research PittsburghPA United States

ISBN: (纸本)9798400711961

Wasm is gaining popularity outside the Web as a well-specified low-level binary format with ISA portability, low memory footprint and polyglot targetability, enabling efficient in-process sandboxing of untrusted code. Despite these advantages, Wasm adoption for new domains is often hindered by the lack of many standard system interfaces which precludes reusability of existing software and slows ecosystem growth. This paper proposes thin kernel interfaces for Wasm, which directly expose OS userspace syscalls without breaking intra-process sandboxing, enabling a new class of virtualization with Wasm as a universal binary format. By virtualizing the bottom layer of userspace, kernel interfaces enable effortless application ISA portability, compiler backend reusability, and armor programs with Wasm’s built-in control flow integrity and arbitrary code execution protection. Furthermore, existing capability-based APIs for Wasm, such as WASI, can be implemented as a Wasm module over kernel interfaces, improving reuse, robustness, and portability through better layering. We present an implementation of this concept for two kernels - Linux and Zephyr - by extending a modern Wasm engine and evaluate our system’s performance on a number of sophisticated applications which can run for the first time on Wasm. © 2025 Copyright held by the owner/author(s).

关键词： program compilers

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TenSet: A Large-scale program Performance Dataset for Learned Tensor compilers 35

TenSet: A Large-scale Program Performance Dataset for Learne...

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35th Conference on Neural Information Processing Systems - Track on Datasets and Benchmarks, NeurIPS Datasets and Benchmarks 2021

作者： Zheng, Lianmin Liu, Ruochen Shao, Junru Chen, Tianqi Gonzalez, Joseph E. Stoica, Ion Haj-Ali, Ameer UC Berkeley United States OctoML United States Carnegie Mellon University United States

Search-based tensor compilers can greatly accelerate the execution of machine learning models by generating high-performance tensor programs, such as matrix multiplications and convolutions. These compilers take a high-level mathematical expression as an input and search for the fastest low-level implementation. At the core of the search procedure is a cost model, which estimates the performance of different implementations to reduce the frequency of time-consuming on-device measurements. There has been a growing interest in using deep learning techniques to learn a cost model to ease the effort of building an analytical model. To realize the potential of such deep learning models, a standard dataset for pre-training and benchmarking learned cost models is necessary. However, this dataset is lacking. We introduce TenSet, a large-scale tensor program performance dataset. TenSet contains 52 million program performance records collected from 6 hardware platforms. We provide comprehensive studies on how to learn and evaluate the cost models, including data collection, model architectures, loss functions, transfer learning, and evaluation metrics. We also show that a cost model pre-trained on TenSet can accelerate the search time in the state-of-the-art tensor compiler by up to 10×. © 2021 Neural information processing systems foundation. All rights reserved.

关键词： program compilers

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