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检索条件"主题词=program compilers"

共 2743 条记录，以下是31-40 订阅

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DialEgg: Dialect-Agnostic MLIR Optimizer using Equality Saturation with Egglog 25

DialEgg: Dialect-Agnostic MLIR Optimizer using Equality Satu...

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23rd ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2025

作者： Zayed, Abd-El-Aziz Dubach, Christophe McGill University Montreal Canada McGill University Mila Montreal Canada

ISBN: (纸本)9798400712753

MLIR’s ability to optimize programs at multiple levels of abstraction is key to enabling domain-specific optimizing compilers. However, expressing optimizations remains tedious. Optimizations can interact in unexpected ways, making it hard to unleash full performance. Equality saturation promises to solve these challenges. First, it simplifies the expression of optimizations using rewrite rules. Secondly, it considers all possible optimization interactions, through saturation, selecting the best program variant. Despite these advantages, equality saturation remains absent from production compilers such as MLIR. This paper proposes to integrate Egglog, a recent equality saturation engine, with MLIR, in a dialect-agnostic manner. This paper shows how the main MLIR constructs such as operations, types or attributes can be modeled in Egglog. It also presents DialEgg, a tool that pre-defines a large set of common MLIR constructs in Egglog and automatically translates between the MLIR and Egglog program representations. This paper uses a few use cases to demonstrate the potential for combining equality saturation and MLIR. © 2025 Copyright held by the owner/author(s).

关键词： program compilers

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Cinnamon: A Framework for Scale-Out Encrypted AI 25

Cinnamon: A Framework for Scale-Out Encrypted AI

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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Jayashankar, Siddharth Chen, Edward Tang, Tom Zheng, Wenting Skarlatos, Dimitrios Carnegie Mellon University PittsburghPA United States

ISBN: (纸本)9798400706981

Fully homomorphic encryption (FHE) is a promising cryptographic solution that enables computation on encrypted data, but its adoption remains a challenge due to steep performance overheads. Although recent FHE architectures have made valiant efforts to narrow the performance gap, they not only have massive monolithic chip designs but also only target small ML workloads. We present Cinnamon, a framework for accelerating state-of-the-art ML workloads that are encrypted using FHE. Cinnamon accelerates encrypted computing by exploiting parallelism at all levels of a program, using novel algorithms, compilers, and hardware techniques to create a scale-out design for FHE as opposed to a monolithic chip design. Our evaluation of the Cinnamon framework on small programs shows a 2.3× improvement in performance compared to prior state-of-the-art designs. Further, we use Cinnamon to show for the first time the scalability of large ML models such as the BERT language model in FHE. Cinnamon achieves a speedup of 36,600× compared to a CPU bringing down the inference time from 17 hours to 1.67 seconds thereby enabling new opportunities for privacy-preserving machine learning. Finally, Cinnamon's parallelization strategies and architectural extensions reduce the required resources per-chip leading to a 5× and 2.68× improvement in performance-per-dollar compared to state-of-the-art monolithic and chiplet architectures respectively. © 2025 ACM.

关键词： program compilers

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Towards Efficient Compiler Auto-tuning: Leveraging Synergistic Search Spaces 25

Towards Efficient Compiler Auto-tuning: Leveraging Synergist...

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23rd ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2025

作者： Pan, Haolin Wei, Yuanyu Xing, Mingjie Wu, Yanjun Zhao, Chen Institute of Software Chinese Academy of Sciences Beijing China Hangzhou Institute for Advanced Study University of Chinese Academy of Sciences Hangzhou China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798400712753

Determining the optimal sequence of compiler optimization passes is challenging due to the extensive and intricate search space. Traditional auto-tuning techniques, such as iterative compilation and machine learning methods, are often limited by high computational costs and difficulties in generalizing to new programs. These approaches can be inefficient and may not fully address the varying optimization needs across different programs. This paper introduces a novel approach that leverages the synergistic relationships between optimization passes to effectively reduce the search space. By focusing on chained synergy pass pairs that jointly optimize a specific target, our method uses K-means clustering to capture common optimization patterns across programs and forms these pairs into coresets. Leveraging a supervised learning model trained on these coresets, we effectively predict the most beneficial coreset for new programs, streamlining the search for optimal sequences. By integrating various search strategies, our method quickly converges to near-optimal solutions. Our approach achieves state-of-the-art performance on ten benchmark datasets, including MiBench, CBench, NPB, and CHStone, demonstrating an average reduction of 7.5% in Intermediate Representation (IR) instruction count compared to Oz. Furthermore, this set of chained synergy pass pairs is also well-suited for iterative search studies by other researchers, as it enables achieving an average codesize reduction of 13.9% compared to Oz with a simple search strategy that takes only about 5 seconds, outperforming existing search-based techniques in the initial pass search space across five datasets. © 2025 Copyright held by the owner/author(s).

关键词： program compilers

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Postiz: Extending Post-increment Addressing for Loop Optimization and Code Size Reduction 25

Postiz: Extending Post-increment Addressing for Loop Optimiz...

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23rd ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2025

作者： Fan, Enming Guan, Xiaofeng Hu, Fan Shi, Heng Zhou, Hao Yao, Jianguo Shanghai Enflame Technology Co. Ltd. Shanghai China Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9798400712753

Memory access instructions with auto-addressing modes are prevalent in various Instruction Set Architectures (ISAs), yet their use in compilers remains limited. Existing methods address code optimization in one of two ways: they either focus on reducing code size, but are constrained to basic block-level optimizations and may not fully exploit architectural benefits, or they optimize loop performance, often neglecting the advantages of post-increment instructions and focusing primarily on innermost loops while leaving outer loops unoptimized. To address these shortcomings and meet the needs of real-world Machine Learning (ML) applications, we introduce Postiz, a novel post-increment loop optimization technique. Postiz extends post-increment optimizations beyond traditional limits, incorporating enhancements for inner loops, cross-loop regions, and nested loop structures. Through a profitability analysis, Postiz optimizes code judiciously, leveraging architectural advantages and reducing code size without compromising improvement made by other optimizations. Our experiments show that Postiz is effective, achieving an optimization coverage of 98.04% on MobileNet and BERT benchmarks. In comparison to default LLVM optimization, Postiz generates approximately four times more post-increment instructions. Moreover, it reduces code size by an average of 9.45% across various platforms. These improvements represent significant advancements over current methods, showcasing Postiz’s potential to enhance compiler optimizations in a meaningful way. © 2025 Copyright held by the owner/author(s).

关键词： program compilers

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APINT: A Full-Stack Framework for Acceleration of Privacy-Preserving Inference of Transformers based on Garbled Circuits 24

APINT: A Full-Stack Framework for Acceleration of Privacy-Pr...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Cho, Hyunjun Jeon, Jaeho Heo, Jaehoon Kim, Joo-Young KAIST Daejeon Korea Republic of

ISBN: (纸本)9798400710773

As the importance of Privacy-Preserving Inference of Transformers (PiT) increases, a hybrid protocol that integrates Garbled Circuits (GC) and Homomorphic Encryption (HE) is emerging for its implementation. While this protocol is preferred for its ability to maintain accuracy, it has a severe drawback of excessive latency. To address this, existing protocols primarily focused on reducing HE latency, thus making GC the new latency bottleneck. Furthermore, previous studies only focused on individual computing layers, such as protocol or hardware accelerator, lacking a comprehensive solution at the system level. This paper presents APINT, a full-stack framework designed to reduce PiT’s overall latency by addressing the latency problem of GC through both software and hardware solutions. APINT features a novel protocol that reallocates possible GC workloads to alternative methods (i.e., HE or standard matrix operation), substantially decreasing the GC workload. It also suggests GC-friendly circuit generation that reduces the number of AND gates at the most, which is the expensive operator in GC. Furthermore, APINT proposes an innovative netlist scheduling that combines coarse-grained operation mapping and fine-grained scheduling for maximal data reuse and minimal dependency. Finally, APINT’s hardware accelerator, combined with its compiler speculation, effectively resolves the memory stall issue. Putting it all together, APINT achieves a remarkable end-to-end reduction in latency, outperforming the existing protocol on CPU platform by 12.2× online and 2.2× offline. Meanwhile, the APINT accelerator not only reduces its latency by 3.3× but also saves energy consumption by 4.6× while operating PiT compared to the state-of-the-art GC accelerator. © 2024 Copyright is held by the owner/author(s).

关键词： program compilers

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OLA: An FPGA-based Overlay Accelerator for Privacy Preserving Machine Learning with Homomorphic Encryption 25

OLA: An FPGA-based Overlay Accelerator for Privacy Preservin...

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33rd ACM/SIGDA International Symposium on Field-programmable Gate Arrays, FPGA 2025

作者： Yang, Yang Kannan, Rajgopal Prasanna, Viktor K. University of Southern California Los AngelesCA United States DEVCOM Army Research Office Los AngelesCA United States

ISBN: (纸本)9798400713965

Homomorphic Encryption (HE) is a promising technique for protecting user privacy in cloud-based Machine Learning (ML) inference. However, homomorphically encrypted operations are orders of magnitude slower than the corresponding unencrypted operations due to high computation and memory bandwidth requirements. FPGAs are attractive platforms for designing domain-specific accelerators. Manually programming FPGAs for HE ML inference is challenging, as different HE parameters and operations require different mapping strategies. We propose OLA, the first FPGA-based overlay accelerator for low latency computation on homomorphically encrypted data. OLA eliminates the need for manual and time consuming FPGA programming by providing a Python-based interface and a compiler that efficiently maps OLA programs to hardware instructions for execution. The hardware architecture and instruction set are co-designed to accelerate common HE primitives, while the compiler maps all the required HE operations to these primitives for efficient execution. OLA features two optimizations to address memory bandwidth challenges in HE computation. First, we propose an asynchronous dataflow execution model where the compiler manages data processing order and the architecture enforces it at run time. This approach enables guaranteed data reuse via on-chip SRAMs. Second, we design latency-aware instruction scheduling in the compiler to reduce data reuse distance. We implement the overlay accelerator on the AMD Alveo U280 FPGA. We evaluate the effectiveness of the proposed overlay accelerator by executing various HE operations, HE linear algebra benchmarks, and end-to-end ML inference. Experimental results show that OLA reduces the latency of HE operations by up to 683× (4.4×) compared with State-Of-The-Art (SOTA) CPU (GPU) implementations. It achieves up to 3212× speedup in latency compared with the SOTA CPU implementations for HE ML inference. © 2025 Copyright held by the owner/author(s).

关键词： program compilers

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CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels 31

CROSS: Compiler-Driven Optimization of Sparse DNNs Using Spa...

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31st IEEE International Symposium on High Performance Computer Architecture, HPCA 2025

作者： Liu, Fangxin Huang, Shiyuan Yang, Ning Wang, Zongwu Li, Haomin Jiang, Li Shanghai Jiao Tong University Department of Computer Science and Engineering China Shanghai Qi Zhi Institute China

ISBN: (纸本)9798331506476

As deep learning models continue to grow larger and more complex, exploiting sparsity is becoming one of the most critical areas for enhancing efficiency and scalability. Several methods for leveraging sparsity have been proposed to more effectively balance the trade-off between compression ratio and accuracy. While these methods offer algorithmic advantages, they also introduce significant hardware overhead due to index-based encoding and decoding. In this paper, we propose CROSS, an end-to-end compilation optimization technique to achieve sparse DNN acceleration using GPU computation kernels. The key insight behind CROSS is to exploit parameter distribution locality and reconcile the 'sparse' DNN computation with the high-performance 'dense' computation kernels. Specifically, we perform an in-depth analysis of sparse operations in mainstream DNN computing frameworks. We then decompose the sparse workload into multiple components to create highly efficient, specialized operators with different sparsity levels. Additionally, we introduce a novel sparse graph translation technique to facilitate computation kernel processing of the sparse workload. The resulting CROSS framework can accommodate various sparsity patterns and optimization techniques, delivering an average 2.03 × speedup on inference latency compared to seven state-of-the-art solutions with smaller memory footprints across various models and datasets. © 2025 IEEE.

关键词： program compilers

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Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning 25

Enhancing CGRA Efficiency Through Aligned Compute and Commun...

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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Li, Zhaoying Dangi, Pranav Yin, Chenyang Bandara, Thilini Kaushalya Juneja, Rohan Tan, Cheng Bai, Zhenyu Mitra, Tulika National University of Singapore Singapore Singapore Peking University Beijing China Google San Francisco United States

ISBN: (纸本)9798400706981

Coarse-grained Reconfigurable Arrays (CGRAs) are domain-agnostic accelerators that enhance the energy efficiency of resource-constrained edge devices. The CGRA landscape is diverse, exhibiting trade-offs between performance, efficiency, and architectural specialization. However, CGRAs often overprovision communication resources relative to their modest computing capabilities. This occurs because the theoretically provisioned programmability for CGRAs often proves superfluous in practical implementations. In this paper, we propose Plaid, a novel CGRA architecture and compiler that aligns compute and communication capabilities, thereby significantly improving energy and area efficiency while preserving its generality and performance. We demonstrate that the dataflow graph, representing the target application, can be decomposed into smaller, recurring communication patterns called motifs. The primary contribution is the identification of these structural motifs within the dataflow graphs and the development of an efficient collective execution and routing strategy tailored to these motifs. The Plaid architecture employs a novel collective processing unit that can execute multiple operations of a motif and route related data dependencies together. The Plaid compiler can hierarchically map the dataflow graph and judiciously schedule the motifs. Our design achieves a 43% reduction in power consumption and 46% area savings compared to the baseline high-performance spatio-temporal CGRA, all while preserving its generality and performance levels. In comparison to the baseline energy-efficient spatial CGRA, Plaid offers a 1.4× performance improvement and a 48% area savings, with almost the same power. © 2025 ACM.

关键词： program compilers

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HyCOMP: A Compiler for ANN-SNN Hybrid Accelerators 25

HyCOMP: A Compiler for ANN-SNN Hybrid Accelerators

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30th Asia and South Pacific Design Automation Conference, ASP-DAC 2025

作者： Zhou, Yitian Li, Yue Hong, Yang Shanghai Jiao Tong Univ. Shanghai China

ISBN: (纸本)9798400706356

The rising energy consumption of Artificial Neural Networks (ANNs) in large-scale computation scenarios has become a critical issue. Spiking Neural Networks (SNNs) offer a promising alternative with their spike-based computation and communication methods. Process-in-memory (PIM) is widely used in SNN acceleration, and is also used to accelerate ANNs to break the memory wall. However, there are few studies on ANN-SNN hybrid network acceleration, which results in several issues. Existing compilers are primarily designed for ANNs or SNNs, with no unified description for hybrid networks. Compilation processes for SNNs vary in focus and lack general phases. Some ANNs hold the potential for conversion to SNNs for energy efficiency, yet their characteristics remain inadequately defined. Thus, we propose HyCOMP - a universal compiler tailored for ANN-SNN hybrid acceleration of PIM architecture. We also design a heuristic algorithm to identify ANNs with energy-efficiency potential. HyCOMP aims to facilitate the mapping of ANNs and SNNs onto distinct acceleration units to enhance energy efficiency. Experiment results on ResNet18, GoogLeNet, VGG16, and Spikformer show that HyCOMP achieves 2.48x and 2.74x improvements in latency and energy consumption respectively compared to the state-of-the-art techniques. © 2025 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

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Asdf: A Compiler for Qwerty, a Basis-Oriented Quantum programming Language 25

Asdf: A Compiler for Qwerty, a Basis-Oriented Quantum Progra...

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23rd ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2025

作者： Adams, Austin J. Khan, Sharjeel Bhamra, Arjun S. Abusaada, Ryan R. Cabrera, Anthony M. Hoechst, Cameron C. Humble, Travis S. Young, Jeffrey S. Conte, Thomas M. Georgia Institute of Technology AtlantaGA United States Oak Ridge National Laboratory Oak RidgeTN United States

ISBN: (纸本)9798400712753

Qwerty is a high-level quantum programming language built on bases and functions rather than circuits. This new paradigm introduces new challenges in compilation, namely synthesizing circuits from basis translations and automatically specializing adjoint or predicated forms of functions. This paper presents Asdf, an open-source compiler for Qwerty that answers these challenges in compiling basis-oriented languages. Enabled with a novel high-level quantum IR implemented in the MLIR framework, our compiler produces OpenQASM 3 or QIR for either simulation or execution on hardware. Our compiler is evaluated by comparing the fault-tolerant resource requirements of generated circuits with other compilers, finding that Asdf produces circuits with comparable cost to prior circuit-oriented compilers. © 2025 Copyright held by the owner/author(s).

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