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检索条件"主题词=program debugging"

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Embedded Hardware Implementation of Noise Gate on STM32 Processor Using MATLAB/Simulink

Embedded Hardware Implementation of Noise Gate on STM32 Proc...

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2024 International Conference on Photonics Solutions, ICPS 2024

作者： Jongsataporn, Thitaphan Chivapreecha, Sorawat Department of Industrial Physic and Medical Instrumentation King Mongkut's University of Technology North Bangkok 1518 Pracharat 1 Road WongsawangBangsue Bangkok10800 Thailand School of Engineering King Mongkut's Institute of Technology Ladkrabang 1 Chalong Krung Lat Krabang Bangkok10520 Thailand

ISBN: (数字)9781510688308

ISBN: (纸本)9781510688292

This paper presents a model-based approach for developing a digital signal processing (DSP) system, specifically focusing on a Noise Gate application, using MATLAB/Simulink, and deploying it on the STM32F769I-Discovery board. The study thoroughly examines the advantages of model-based hardware implementation, particularly in facilitating rapid prototyping for real-time applications in educational contexts. The STM32F769I is powered by a high-performance Arm® Cortex®-M7 core, which can execute DSP instructions efficiently. Its ample memory and built-in debugging tools enhance its suitability for complex signal processing tasks. The implementation leverages MATLAB/Simulink and its robust compatibility with the STM32 hardware, allowing for seamless software and hardware component integration. The powerful model-based development features streamline the transition from simulation to physical hardware, reducing development time and enhancing reliability. The Noise Gate application is designed to control audio signals effectively, eliminating unwanted background noise through user-defined parameters such as threshold, attack time, and release time, which optimize performance based on specific audio environments. Additionally, the design applies a first-order IIR low-pass as a smoothing filter, which dynamically adjusts the gain according to the characteristics of the incoming audio signal. This ensures gradual opening and closing of the gate, resulting in smoother audio transitions. The results demonstrate significant noise suppression and overall audio quality enhancement, highlighting the practicality of employing model-based design methodologies for DSP applications. Furthermore, the insights gained from this study contribute to efficient hardware prototype development and offer implications for future projects in the field of digital signal processing. © 2025 SPIE.

关键词： program debugging

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debugging of java programs using HDT with program slicing

Debugging of java programs using HDT with program slicing

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International Conference on Computational Science and its Applications, ICCSA 2004

作者： Kouh, Hoon-Joon Kim, Ki-Tae Jo, Sun-Moon Yoo, Weon-Hee School of Computer Information Technology Kyungin Women’s College #101 GyeSan Dong GyeYang Ku Incheon Korea Republic of Dept. of Computer Science and Engineering Inha University #253 YongHyun Dong Nam Ku Incheon Korea Republic of

ISBN: (纸本)3540220607

In the previous work, we presented HDT for debugging logical errors in Java programs. The HDT locates an erroneous function at an execution tree using an algorithmic program debugging and locates a statement with errors in the erroneous function using a step-wise program debugging. It reduced the number of programmer debugging in Java programs. But the HDT still increases the number of debugging because the size of the recent programs increases than the past programs and the number of methods is increasing. This paper proposes HDTS using a program slicing technique (PST) at the HDT. When programmers debug a Java program with HDTS, the PST can reduce the number of programmer debugging. © Springer-Verlag Berlin Heidelberg 2004.

关键词： program debugging

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Enabling Efficient Mobile Tracing with BTrace 25

Enabling Efficient Mobile Tracing with BTrace

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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Wang, Jiawei Liu, Nian Casadevall-Saiz, Arnau Liu, Yutao Behrens, Diogo Fu, Ming Jia, Ning Härtig, Hermann Chen, Haibo Huawei Dresden Research Center Dresden Germany Huawei Central Software Institute Hangzhou China Technische Universität Dresden Dresden Germany Vrije Universiteit Brussel Brussel Belgium Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9798400710797

With the growing complexity of smartphone systems, effective tracing becomes vital for enhancing their stability and optimizing the user experience. Unfortunately, existing tracing tools are inefficient in smartphone scenarios. Their distributed designs (with either per-core or per-thread buffers) prioritize performance but lead to missing crucial clues with high probability. While these problems can be overlooked in previous scenarios (e.g., servers), they drastically limit the usefulness of tracing on smartphones. To enable efficient tracing on smartphones, we propose BTrace: a tracing tool that combines the performance benefits of per-core buffers with the capability of retaining longer continuous traces by partitioning a global buffer into multiple blocks, which are dynamically assigned to the most demanding cores. BTrace further gracefully handles unique requirements of modern smartphones, e.g., core oversubscription and resizing. BTrace has been deployed in production, recording an average of 2x continuous traces compared to the current best-performing tracer (Linux ftrace) and improving performance by 20%. Using BTrace, we successfully identified numerous bugs that require traces of long duration and are challenging to locate with existing tracers. © 2025 ACM.

关键词： program debugging

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Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration 25

Hercules: Efficient Verification of High-Level Synthesis Des...

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33rd ACM/SIGDA International Symposium on Field-programmable Gate Arrays, FPGA 2025

作者： Xu, Shuoxiang Jiang, Zijian Zhang, Yuxin Boland, David Bao, Yungang Shi, Kan Institute of Computing Technology Chinese Academy of Sciences ShanghaiTech University Beijing China State Key Lab of Processors Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing China Beijing Insititute of Open Source Chip Beijing China The University of Sydney Sydney Australia

ISBN: (纸本)9798400713965

High-Level Synthesis (HLS) enables software engineers to create intricate digital circuit designs using high-level languages like C/C++. While HLS tools can perform functional verification using C/C++ simulation, it is harder to verify that the generated RTL is also correct. This problem is exacerbated for designs which include HLS-generated IPs, such as PCIe or DDR interfaces, or hand-written RTL. While it is possible to perform cycle-accurate verification using C/RTL co-simulation, conventional methods are both slow and typically only focus on unit-level verification which can make it harder to identify the root cause of a bug. To improve hardware verification, we propose Hercules: a novel method to efficiently verify HLS designs while preserving fine-grained debugging capabilities. HLS-generated hardware and corresponding C/C++ software models are run simultaneously on the FPGA’s programmable logic and hardened processors respectively. We compare both results of the hardware and software, and also compare internal signals with the help of the automatically generated probes to identify bugs and their root causes. This capability is embedded within a tool that takes hardware snapshots, meaning to debug the design we can recreate a software simulation from a point shortly before where the bug occurred. With Hercules, we have performed verification quickly over large benchmarks. This has helped us find HLS errors closer to their root cause than existing tools, making it easier to debug, as well as identify real issues in existing benchmarks and the Vitis HLS tool which current state-of-the-art methods were unable to locate. Moreover, it achieves this quickly - over a set of HLS benchmarks Hercules achieves speedups with a geometric mean ranging from 1391× to 8060× compared to conventional software simulations. © 2025 Copyright held by the owner/author(s).

关键词： program debugging

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Test Case Generation Techniques for Fault Root Cause Localization 24

Test Case Generation Techniques for Fault Root Cause Localiz...

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3rd International Conference on Signal Processing, Computer Networks and Communications, SPCNC 2024

作者： Du, Hao Gao, Chengshan Ma, Zhaotun Zhongxun Post and Telecommunications Consulting and Design Institute Henan Zhengzhou China

ISBN: (纸本)9798400710834

Fault root cause localization is a critical phase in software debugging, and spectrum-based fault localization methods represent a focal point in research on automated software debugging. However, the effectiveness of these methods largely hinges on the quality of the test cases. The generic applicability of test inputs varies significantly across different types of software, while randomly generated test inputs often suffer from overfitting or excessive noise, leading to significant errors in the analysis results, which limits the practical application scenarios of such technologies. To address the issues in test case generation, this paper proposes a staged exploration method based on crash paths, named Dgenerate. Firstly, binary instrumentation is employed to instrument path information at the basic block level during the program’s input execution phase. Based on this information, the original test inputs are categorized into ordinary and guiding types. Subsequently, a dynamic energy scheduling algorithm is utilized to explore crash-related paths, generating high-quality test cases. Finally, the test cases are executed on the original program, and runtime information is traced. Statistical analysis is then applied to effectively pinpoint the location of the program faults. We conducted experiments on fifteen real-world CVE vulnerabilities from six different types of software. The results show that the test cases generated by Dgenerate can improve the localization efficiency by 75% on average compared to the previous techniques, which verifies the feasibility and practicability of the method in this paper. © 2024 Copyright held by the owner/author(s).

关键词： program debugging

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Connectivity Certificate against Bounded-Degree Faults: Simpler, Better and Supporting Vertex Faults 8

Connectivity Certificate against Bounded-Degree Faults: Simp...

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8th SIAM Symposium on Simplicity of Algorithms, SOSA 2025

作者： Parter, Merav Tzalik, Elad Weizmann Institute Israel

ISBN: (纸本)9781611978315

An f-edge (or vertex) connectivity certificate is a sparse subgraph that maintains connectivity under the failure of at most f edges (or vertices). It is well known that any n-vertex graph admits an f-edge (or vertex) connectivity certificate with Θ(fn) edges (Nagamochi and Ibaraki, Algorithmica 1992). A recent work by (Bodwin, Haeupler and Parter, SODA 2024) introduced a new and considerably stronger variant of connectivity certificates that can preserve connectivity under any failing set of edges with bounded degree. For every n-vertex graph G = (V, E) and a degree threshold f, an f-Edge-Faulty-Degree (EFD) certificate is a subgraph H ⊆ G with the following guarantee: For any subset F ⊆ E with deg(F) ≤ f and every pair u, v ∈ V, u and v are connected in H − F iff they are connected in G − F. For example, a 1-EFD certificate preserves connectivity under the failing of any matching edge set F (hence, possibly |F| = Θ(n)). In their work, [BHP'24] presented an expander-based approach (e.g., using the tools of expander decomposition and expander routing) for computing f-EFD certificates with O(fn·poly(log n)) edges. They also provided a lower bound of Ω(fn · logf n), hence Ω(n log n) for f = O(1). In this work, we settle the optimal existential size bounds for f-EFD certificates (up to constant factors), and also extend it to support vertex failures with bounded degrees (where each vertex is incident to at most f faulty vertices). Specifically, we show that for every n > f/2, any n-vertex graph admits an f-EFD (and f-VFD) certificates with O(fn·log(n/f)) edges. Our upper bound arguments are considerably simpler compared to prior work, do not use expanders, and only exploit the basic structure of bounded degree edge and vertex cuts. Copyright © 2025 by SIAM.

关键词： program debugging

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The Design of a Multi-application Micro-operating System Platform in the Context of Big Data 6th

The Design of a Multi-application Micro-operating System Pla...

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6th International Conference on Security and Privacy in New Computing Environments, SPNCE 2023

作者： Mo, Wenpan Shen, Zhicheng Eastcompeace Technology Co. Ltd. Guangdong Zhuhai China

ISBN: (纸本)9783031736988

In the context of big data, the security problem of smart card operating system is realized independently and controllably, For smart cards and the internet of things, a multi-application microoperating system platform is proposed. The platform’s operating system is based on the virtual machine technology to support the dynamic loading, installation, deletion, and interpretation of the execution of applications, the virtual machine adopts a register-based instruction set architecture, the interpreter is faster, and the instruction optimization is easier. At the same time, the platform provides an application compiler to realize the generation of execution files running in micro-operating systems from source code parsing, compilation, and linking, which supports a variety of programming languages to develop applications, and generates register-based instruction set bytecode EF files after compilation and linking. The platform also provides a set of integrated tools integrated into application source code development, compilation, and loading of applications to virtual OS (or real OS) for application operation, testing, and debugging. Experimental results show that the proposed multi-application microoperating system has good running speed and has the ability to protect high-value and high-sensitive information, and the ability to provide high-level security protection for the device, and provide related tools such as source code development, compilation, run, testing, and debugging of applications, this improves the efficiency of application development, testing, and debugging. © ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 2025.

关键词： program debugging

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A High Precision Optical-Fiber Temperature Sensor Based on Fluorescence Lifetime 2

A High Precision Optical-Fiber Temperature Sensor Based on F...

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2nd International Conference on Engineering of Optical Systems and Precision Instruments, ICEOP 2024

作者： Yang, Yuxuan Yang, Jian Cao, Zhixiang Jin, Xiangliang School of Physics and Electronics Hunan Normal University Changsha China Key Laboratory of Physics and Devices in Post-Moore Era College of Hunan Province Changsha China

Optical-fiber temperature sensors have the advantages of strong anti-interference and high accuracy, which are widely used in industrial production, while fluorescence lifetime is a common parameter for indirect temperature measurement. In this paper, a small high precision optical-fiber temperature sensor based on fluorescence lifetime is designed and samples are fabricated. In order to improve the acquisition accuracy of fluorescence lifetime, the software and hardware parts were designed and debugged. In terms of algorithm, the weighted least squares method is used to fit the decay curve of the fluorescence signal and calculate the fluorescence lifetime. Finally, the temperature calibration test was carried out in a high and low temperature thermostat. The test results show that comparing with the integral ratio method, this paper can reduce the measurement error of fluorescence lifetime by 69.7% on average, which effectively improves the precision of fluorescence lifetime. This not only verifies the effectiveness of the sensor in obtaining high precision fluorescence lifetime, but also facilitates the improvement of temperature resolution. © 2025 Institute of Physics Publishing. All rights reserved.

关键词： program debugging

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Videogamebunny: Towards Vision Assistants for Video Games

Videogamebunny: Towards Vision Assistants for Video Games

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2025 IEEE/CVF Winter Conference on Applications of Computer Vision, WACV 2025

作者： Taesiri, Mohammad Reza Bezemer, Cor-Paul University of Alberta Canada

ISBN: (纸本)9798331510831

Large multimodal models (LMMs) hold substantial promise across various domains, from personal assistance in daily tasks to sophisticated applications like medical diagnostics. However, their capabilities have limitations in the video game domain, such as challenges with scene understanding, hallucinations, and inaccurate descriptions of video game content, especially in open-source models. This paper describes the development of VideoGameBunny,a LLaVA-style model based on Bunny, specifically tailored for understanding images from video games. We release intermediate checkpoints, training logs, and an extensive dataset comprising 185,259 video game images from 413 titles, along with 389,565 image-instruction pairs that include image captions, question-answer pairs, and a JSON representation of 16 elements of 136,974 images. Our experiments show that our high quality game-related data has the potential to make a relatively small model outperform the much larger state-of-the-art model LLaVa-1.6-34b (which has more than 4x the number of parameters). Our study paves the way for future research in video game understanding on tasks such as playing, commentary, and debugging. Code and data are available at: https://***/ © 2025 IEEE.

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program Structure Defect Localization and Repair Methods in Software Security Reverse Analysis

Program Structure Defect Localization and Repair Methods in ...

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6th International Conference on Cyber Security Intelligence and Analytics, CSIA 2024

作者： Li, Yan Wuhan Qingchuan University Wuhan Hubei China

ISBN: (纸本)9783031882869

In the field of software security, program structure defects are the main cause of system vulnerability and attack. Especially when the software is very complicated, bug localization and repair become particularly difficult. The aim of the article is to analyze reverse debugging, program structure defect mining, location and repair methods, and enhance the security and stability of software. The binary code is first processed through a combination of several reverse tools, static analysis tools SonarQube and Checkmax to find out potential program structure defects, and then pass the combination of dynamic symbol execution and fuzzy testing method to monitor the behavior of the program during runtime, in order to further verify defects found by static analysis, and to detect new defects generated during runtime. The effectiveness of the method is further evinced by an experiment using 100 open source software. In most cases, the detection rate of static analysis method for structure defects is 78%, while dynamic analysis on the cloud actually confirms that 92% of these defects are true, so reverse debugging fully satisfies the requirement of using the value stored in the register ESP of the local stack to locate the position on the reference source. After passing the run, the pass rate of software in security testing increases from 85% to 95%, indicating that the application of the method can increase the security and reliability of software. The integrated method can locate and repair buggy structure defects of a program, so that the software has fewer security flaws, and better quality. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

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