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Scheduling Architecture-Supported Regions in Parallel programs

Scheduling Architecture-Supported Regions in Parallel Progra...

10th Nordic International Conference on Applied Parallel Computing - State of the Art in Scientific and Parallel Computing (PARA)

作者： Tudruj, Marek Masko, Lukasz Polish Acad Sci Inst Comp Sci PL-01237 Warsaw Poland

ISBN: (纸本)9783642281501;9783642281518

Current multicore system technology enables implementation of particular program functions like library operations, special functions generation, optimized data search etc. using dedicated computing units to increase overall program performance. A parallel system can be equipped with a set of such units to speed up execution of applications, which use such functionality. To properly model and schedule programs using such functions running on a dedicated hardware, a proper program representation must be introduced. The paper presents special scheduling algorithm for programs represented as graphs, based on a modified ETF heuristics. The algorithm is meant for a modular architecture composed of many CMP modules interconnected by a global data communication network. The assumed architecture of dedicated CMP modules enables personalized fully synchronous program execution, which uses communication on the fly to strongly reduce inter-core communication overheads.

关键词： CMP architectures program execution control program scheduling data communication optimization

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Multi-CMP system with data communication on the fly

引用

JOURNAL OF SUPERCOMPUTING 2011年第1期57卷 51-64页

作者： Tudruj, Marek Masko, Lukasz Thor, Miroslaw Polish Acad Sci Inst Comp Sci PL-01237 Warsaw Poland Polish Japanese Inst Informat Technol PL-02008 Warsaw Poland Telemark Univ Coll N-3800 Bo I Telemark Norway

The paper concerns new communication solutions for hierarchical Chip Multiprocessor (CMP) systems composed of many CMP modules interconnected by a global data exchange network. New architectural solutions for internal module data communication are presented in the presence of hierarchical data caches in CMP modules. Inside CMP modules, dynamic shared memory core clusters are organized around L1-L2 data cache busses. Such clusters enable a group-oriented data communication based on reads on the fly to L1 banks of data present on the busses by many cores at a time. Dynamic switching of cores between such L1-L2 busses is done with porting data in core's L1 caches. Together with data reads on the fly, it provides a very efficient intercluster "communication on the fly," especially useful for transfers of strongly shared data. It provides fast cache to cache group data transmissions and eliminates standard transactions based on shared memory in the system. Comparative experimental results based on automatic scheduling of program data flow graphs and execution in a simulator of the proposed architecture evaluate the assumed architectural solutions. The multi-CMP system structure is assessed while taking into account technological limitations of the size of the single CMP module.

关键词： Modular CMP systems program execution control Dynamic shared memory clusters Communication on the fly

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