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10th Latin American Conference on High Performance Computing (CARLA)

作者： Perdomo, Diego A. Roa Guaitero, Rafael A. Herrera Fox, Dawson Yviquel, Herve Raskar, Siddhisanket Li, Xiaoming Diaz, Jose M. Monsalve Argonne Natl Lab Argonne IL 60439 USA Univ Delaware Newark DE 19716 USA Univ Estadual Campinas Campinas Brazil

ISBN: (纸本)9783031521850;9783031521867

Failure or disruption in High-Performance Computer Systems can have a significant impact on human life, the environment, or the economy. Critical applications refer to software systems or functionalities that are essential for the safety, security, or continuity of critical infrastructure, services, or operations. Considering that semiconductor devices are susceptible to errors and failure, providing error detection and correction mechanisms in such systems is imperative. However, the main challenge for achieving fault tolerance and resiliency is compartmentalizing the causes and the consequences of error, in both hardware and software. Moreover, today's extreme-scale parallel HPC systems necessitate fundamentally non-deterministic executions, making compartmentalization an even bigger challenge. To address these challenges, this paper proposes leveraging the Sequential Codelet model (SCM), which facilitates parallel execution of programs expressed sequentially and hierarchically. We propose to exploit SCM's encapsulation of semantics and data to compartmentalize faults transparently and efficiently. We present multiple techniques that can be implemented in the Sequential Codelet model to include fault-tolerant and resiliency mechanisms. We implement already-known solutions by extending a functional emulator for the Sequential Codelet model.

关键词： Codelet model program execution model Fault Tolerance Resiliency

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DEMAC: A Modular Platform for HW-SW Co-Design 4

DEMAC: A Modular Platform for HW-SW Co-Design

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IEEE/ACM 4th Annual Workshop on Emerging Parallel and Distributed Runtime Systems and Middleware (IPDRM)

作者： Perdomo, Diego A. Roa Kabrick, Ryan Diaz, Jose M. Monsalve Raskar, Siddhisanket Fox, Dawson Gao, Guang R. Univ Delaware Newark DE 19716 USA Argonne Natl Lab Lemont IL USA

ISBN: (纸本)9780738110646

Scientists running applications on high performance computers expect these systems to deliver a high throughput effectively and reliably, while maintaining flexibility, programmability and energy efficiency. programs are usually translated from a coded language that defines the operation of these systems through a compiler. HPC machines exhibit different features and behaviors based on their architectural characteristics: they could have accelerators or be a collection of computational units with a non-uniform memory access. Aiming to develop a low-cost, flexible and versatile parallel machine for hardware-software co-design of program execution models research, we present DEMAC (the Delaware Modular Assembly Cluster). It provides the necessary tools to develop and test novel features for the next generation of supercomputers. It includes a set of 3D-printed frames that can house several card-sized multi-core embedded systems. Along with a full open source stack, these small computers feature Parallella boards containing a Zynq-7000 series SoC with a dual-core ARM processor and an FPGA that interconnects with a 16-core co-processor called Epiphany. All individual nodes are connected through an Ethernet network. An initial version of a runtime based on Dataflow's Codelet model is also proposed. This project aims to provide a flexible research platform that could benefit different research labs looking for low-cost parallel platforms.

关键词： Dataflow model Codelet model program execution model DARTS Many-core architecture Cluster Software-Hardware Co-design FPGA Exa-scale

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CODIR: Towards an MLIR Codelet model Dialect 4

CODIR: Towards an MLIR Codelet Model Dialect

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IEEE/ACM 4th Annual Workshop on Emerging Parallel and Distributed Runtime Systems and Middleware (IPDRM)

作者： Kabrick, Ryan Perdomo, Diego A. Roa Raskar, Siddhisanket Diaz, Jose M. Monsalve Fox, Dawson Gao, Guang R. Univ Delaware Newark DE 19716 USA

ISBN: (纸本)9780738110646

Since IBM first introduced the Instruction Set Architecture (ISA), there has been tremendous research conducted on novel hardware architectures and new high-level software frameworks, perhaps to a fault. With innovation came an ever growing gap between a program's description and how it is executed on hardware. Successful exploitation of these innovations calls for a unifying contract to be in place which distinguishes the program description from the low-level execution on target hardware;namely, a program execution model (PXM). By decoupling the programming API from the hardware description the obstacles imposed by low-level architectures and high-level language interoperability are avoided by utilizing program manipulation, source-level optimizations, and eventual lowering into machine code across a wide variety of different heterogeneous hardware. To achieve these goals in software, compilers must adapt to the ever-changing climate of hardware and software development. They must be able to represent data at varying levels so as to provide maximum opportunities for optimizations based on information which would otherwise be lost without utilizing progressive lowering. The target hardware should also not limit the amount of possible software-based optimizations. We propose CODIR, the Codelet model domain-specific language extension and intermediate representation built using the already existing Multi-Level Intermediate Representation (MLIR) compiler infrastructure. It aims to progressively lower a high-level language to an intermediate representation well suited for maximizing optimization opportunities available to the compiler while additionally providing a plethora of hardware support. Underlying CODIR is the Codelet model which we believe to be a sound program execution model for mapping computation to the machine and utilizing all available hardware resources.

关键词： Dataflow model Codelet model program execution model DARTS Many-core architecture Software-Hardware Co-design Exa-scale Compiler Machine Learning

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Position Paper: Extending Codelet model for Dataflow Software Pipelining using Software-Hardware Co-Design 43

Position Paper: Extending Codelet Model for Dataflow Softwar...

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43rd IEEE-Computer-Society Annual International Computers, Software and Applications Conference (COMPSAC)

作者： Raskar, Siddhisanket Applencourt, Thomas Kumaran, Kalyan Gao, Guang Argonne Natl Lab Lemont IL 60439 USA Univ Delaware Newark DE 19716 USA

ISBN: (纸本)9781728126074

Trends in processor and system architecture, driven by power and complexity, point super-computing landscape toward very high and heterogeneous core count designs. As the number of cores inevitably increase traditional ways of performing large scale computations will also need to evolve from legacy models like OpenMP & MPI. However, such models are very much wedded to a control-flow vision of parallel programs, making it difficult to express asynchrony in programs. To address these challenges, codelet model was developed which is fine-grained, event-driven asynchronous program execution model. In-spite of its initial design goals, the Codelet model is rife with opportunities for further improvements to provide high-performance for both data and control regular applications. The major inspiration behind this work is to leverage the decades of research done to exploit instruction level parallelism (ILP) for the machine instructions inside codelet while build upon the dataflow software pipelining principals at codelet graph level to further enhance performance. In this paper, we propose hardware assisted extensions to the original codelet program execution model in order to implement efficient dataflow software pipelining and extend capabilities of the codelet model. This hardware-software co-design focuses on efficient implementation of data FIFO buffers leveraging proposed optimizations like - FIFO ring buffers and multiple-head FIFO buffers and single owner FIFO buffers to further exploit advantages of dataflow software pipelining. The wide range of scientific, machine learning and specially streaming applications should be able to take advantage of techniques proposed in this paper. Identifying these kernels and bench-marking them are the next anticipated steps for us.

关键词： Dataflow model Software Pipelining Dataflow Software Pipelining Codelet model program execution model Many-core Architecture FIFO Buffer Exa-scale

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Principles to Support Modular Software Construction

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Journal of Computer Science & Technology 2017年第1期32卷 3-10页

作者： Jack B. Dennis Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA 02139 U.S.A.

The construction of large software systems is always achieved through assembly of independently written components -- program modules. For these software components to work together, they must share a common set of data types and principles for representing structured data such as arrays of values and files. This common set of tools for creating and operating on data objects is provided by the infrastructure of the computer system： the hardware, operating system and runtime code. Because the nature and properties of these tools are crucial for correct operation of software components and their inter-operation, it is essential to have a precise specification that may be used for verifying correctness of application software on one hand, and to verify correctness of system behavior on the other. We call such a specification a program execution model （PXM）. It is evident that the properties of the PXM implemented by a computer system can have serious impact on the ability of application programmers to practice modular software construction. This paper discusses the concept of program execution models and presents a set of principles that a PXM must satisfy to provide a sound basis for modular software construction. Because parallel program execution on computer systems with many processing units is an essential part of contemporary computing environments, the expression of parallelism and modular software construction using components involving parallel operations is included in this treatment. The conclusion is that it is possible to build computer systems that implement a PXM within which any parallel program may be used, unmodified, as a component for building more substantial parallel programs.

关键词： program execution model data flow model codelet abstract architecture parallel computing

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Using a "codelet" program execution model for exascale machines: position paper 11

Using a "codelet" program execution model for exascale machi...

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Proceedings of the 1st International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era

作者： Stéphane Zuckerman Joshua Suetterlein Rob Knauerhase Guang R. Gao University of Delaware Intel Labs

ISBN: (纸本)9781450307086

As computing has moved relentlessly through giga-, tera-, and peta-scale systems, exa-scale (a million trillion operations/sec.) computing is currently under active research. DARPA has recently sponsored the "UHPC" [1] --- ubiquitous high-performance computing --- program, encouraging partnership with academia and industry to explore such systems. Among the requirements are the development of novel techniques in "self-awareness"in support of performance, energy-efficiency, and *** in processor and system architecture, driven by power and complexity, point us toward very high-core-count designs and extreme software parallelism to solve exascaleclass problems. Our research is exploring a fine-grain, event-driven model in support of adaptive operation of these machines. We are developing a Codelet program execution model which breaks applications into codelets (small bits of functionality) and dependencies (control and data) between these objects. It then uses this decomposition to accomplish advanced scheduling, to accommodate code and data motion within the system, and to permit flexible exploitation of parallelism in support of goals for performance and power.

关键词： exascale program execution model manycore dataflow

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Towards a codelet-based runtime for exascale computing: position paper 12

Towards a codelet-based runtime for exascale computing: posi...

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Proceedings of the 2nd International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era

作者： Christopher Lauderdale Rishi Khan ET International Inc.

ISBN: (纸本)9781450311472

Computing systems have reached the performance limits attainable by increasing clock rates and complexity, and are now using increased thread-level parallelism and heterogeneity instead. Existing software typically deals poorly with large-scale or heterogeneous computer systems, relying on multiple poorly interacting or special-purpose software interfaces to approach scaling/heterogeneity; attempting to use these approaches on future computers (especially at exascale) will only make matters *** solve this problem, software components may be broken up into pieces, called "codelets", that can be dynamically scheduled without reliance on binding to any one thread or hardware component in relation to other codelets. By placing a supporting runtime layer between the system interface and codelet-based application, a very high degree of parallelism can be exposed, scaled, and scheduled to use the available hardware efficiently and intelligently. A codelet-based runtime can be used to create a clear path forward to exascale, as well as to deal with computing challenges in the interim.

关键词： adaptive dynamic codelet runtime program execution model exascale parallel many-core

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The compiler for supporting multithreading in cyclic register windows

The compiler for supporting multithreading in cyclic registe...

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2nd International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 96)

作者： Li, C Wang, DX Shen, MM Zheng, WM Peng, SL TSING HUA UNIV DEPT COMP SCI & TECHNOLBEIJING 100084PEOPLES R CHINA

ISBN: (纸本)0818674601

This paper presents the compilation technique to support the P&M (pipelining and multithreading) multithreaded program execution model on the SPARC processor, which has cyclic register windows. The program execution model improves the performance by running multiple user-level threads on each processor and filling the idle cycles that would otherwise be wasted waiting for messages. The integrated compilation paradigm is described systematically. The generated code is efficient, which obtains rapid context switching without sacrificing the benefit of fast procedure call.

关键词： program compilers parallel processing performance evaluation compiler multithreading cyclic register windows multithreaded program execution model SPARC processor program execution model performance idle cycles rapid context switching fast procedure call

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PROVING programS TO BE CORRECT

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IEEE TRANSACTIONS ON COMPUTERS 1971年第11期C 20卷 1331-&页

作者： KING, JC IBM Thomas J. Watson Research Center Yorktown Heights NY USA

This paper formally describes a technique for proving that computer programs will always execute correctly. In order to do this, an abstract model for a program and its execution is given. Then, correctness of program... 详细信息

关键词： Abstract programs debugging program correctness program execution model state vector theory of programming.

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