In this work, a test chip for a 32 channel ultrasound imaging digitizer for intra-cardiac echocardiography is presented. The focus of this design is on area-and power efficiency, as well as multi-purpose usage for var...
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In this work, a test chip for a 32 channel ultrasound imaging digitizer for intra-cardiac echocardiography is presented. The focus of this design is on area-and power efficiency, as well as multi-purpose usage for various catheters. It contains 32 individual analogfront-ends and 12 bit SAR ADCs operating at 40MS/s to enable off-chip digital beamforming. The analogfront-end is programmable in power, bandwidth, gain and can be partially bypassed. The front-end bypass and slew-rate can be dynamically adjusted to save power during a receive period. On-chip supply regulation is included, which can be duty-cycled between receive periods to power down the system and save power. This leads to a power supply consumption between 4.5 and 14.1mW when always on, or between 0.37 and 1.15mW when duty-cycling at an 8% ratio. When operating at maximum power, an SFDR of 57.5dB and SNR of 56.1dB are *** ADC performance can optionally be improved by clocking the array in 4 separate clock phases, resulting in lower peak currents, less power supply disturbance and an overall linearity improvement of 6dB. The 32 channel array occupies 1mm(2) including decoupling capacitance, combining low area and low power operation.
This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled...
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ISBN:
(纸本)9781424492701
This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable Sigma Delta ADC. The full system is designed in UMC 0.18 mu m CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47 mu W power consumption. The ADC provides 2nd order noise-shaping while using single integrator and an ENOB of similar to 11 bits with 5 mu W power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices.
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