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37th International Conference on VLSI Design (VLSID) / 23rd International Conference on Embedded Systems (ES)

作者： Chakraborty, Kuntal Pandey, Jai Gopal Mondal, Abir J. NIT Arunachal Pradesh Elect & Commun Engn Jote India CSIR CEERI Integrated Circuits & Syst Grp Pilani Rajasthan India

ISBN: (纸本)9798350384406

This work presents a programmable delay cell in 90- nm CMOS technology and 1.1 V supply voltage Vdd. The delay cell provides the variable delay option with eight different modes M0-M7 and maintaining a stable output. Neglecting bond pad and die decoupling capacitor, the structure occupies 0.009 mm(2). The proposed delay cell consumes only 0.671 mu W at MO and 3.88 mu W at M7. Besides, for NN process the delay corresponding to the modes ranges between 0.69 - 5.54 mu s at 1.1 V and 27 degrees C. The results of Monte Carlo study show that power and delay changes minimally for MO and are equal for M7 to that obtained at NN.

关键词： programmable delay delay chain multiplexer channel length modulation coefficient

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Design of a 4-bit programmable delay with TDC-based BIST for Use in Serial Data Links 14

Design of a 4-bit Programmable Delay with TDC-based BIST for...

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14 International Symposium on Integrated Circuits (ISIC)

作者： Mehrabi, Taha Raahemifar, Kaamran Geurkov, Vadim Ryerson Univ Elect & Comp Engn Dept Toronto ON Canada

ISBN: (纸本)9781479948338

Time mode signal processing (TMSP) in general is defined as the manipulation of sampled analog signal information using time difference variable. TMSP allows one to implement analog signal processing functions using the most basic element available, namely, propagation delay. A time to digital converter (TDC) is used to convert the time difference between two edges of two signals into a sequence of digital numbers. TDCs have been extensively used in designing laser range finders, all digital phase locked loops (ADPLL), frequency synthesizers, analog to digital converters (ADC), SerDes, etc. This paper proposes a new approach that utilizes a TDC for detection of potential stuck-at faults in a 4-bit programmable delay to be used in designing a time mode SerDes. Moreover, the proposed approach suggests that, when any circuit needs to delay a certain signal, it can be confirmed whether the amount of delay is correctly enforced by utilizing a TDC module and translating the difference between the main signal and the delayed version of the signal into a sequence of bits. Then, one can observe if the generated bits correspond to a correct operation of the circuitry in charge of delaying the main signal.

关键词： built-in self test circuit testing delay circuits fault diagnosis programmable circuits signal generators time-digital conversion ADC ADPLL TDC-based BIST TMSP all digital phase locked loop analog signal processing function analog to digital converter frequency synthesizer laser range finder potential stuck-at fault detection programmable delay propagation delay sampled analog signal information serial data link signal sequence time difference variable time mode SerDes time mode signal processing time to digital converter word length 4 bit Integrated circuits analog digital converter Built-in self test laser range finders delay circuits programmable circuits circuit testing frequency synthesizers Signal generators Propagation delay all digital phase-locked loop Signal Peptides Fault diagnosis programmable delay TimeDif Transcranial Direct Current Stimulation

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A Configurable CMOS delay Element for Spiking Neural Networks

A Configurable CMOS Delay Element for Spiking Neural Network...

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2024 International Conference on Microelectronics-ICM

作者： Lawrence, Dan Muralidhar, Bharath Kumar Singh Rieger, Robert Univ Kiel Chair Networked Elect Syst Kiel Germany

ISBN: (纸本)9798350379402;9798350379396

This paper presents a comparison of various implementations used to generate configurable delays in spiking patterns using a PIC16F18446 microcontroller. We compare their characteristics and respective trade-offs, focusing on delay ranges up to 100 ms and analyzing memory utilization and jitter for each method. Additionally, we introduce an analog delay element that provides programmable delays in biological ranges for spiking neural signals. The proposed circuit handles bursting spike patterns at frequencies up to 1 kHz and is designed and simulated in CMOS 350nm technology, with a power dissipation of 94.68 mu W for a 1 ms delay and a chip area of 152x92.6 mu m(2).

关键词： programmable delay Spiking neurons microcontroller CMOS-based technology delay cell

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A high-resolution all-digital pulse-width modulator architecture with a tunable delay element in CMOS

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2020年第8期48卷 1329-1345页

作者： Morales, Juan Ignacio Chierchie, Fernando Mandolesi, Pablo Sergio Paolini, Eduardo Emilio Univ Nacl Sur Dept Ingn Elect & Comp Inst Invest Ingn Elect IIIE Alfredo Desages CONICET Av Alem 1253 B8000CPB Bahia Blanca Buenos Aires Argentina Comis Invest Cient Provincia Buenos Aires CIC Buenos Aires DF Argentina

A design for an all-digital high-resolution pulse-width modulator (HRPWM) architecture is presented in this work. The architecture is based on a novel digitally controlled delay element that combines two different approaches, achieving a variable time interval up to 54 ps, and adjustable against process, voltage, and temperature (PVT) variations. The proposed system uses several delay elements with a counter-based digital pulse-width modulator (DPWM) in a hybrid configuration, which allows to obtain duty cycles with 18-bit resolution without using a high-frequency internal clock and maintaining a low power dissipation. The HRPWM was implemented in a standard low-cost 130-nm CMOS technology, together with a memory used to store the duty cycles, and a serial communication module. Post layout simulation results show good linearity between the control word and the duty cycle in all the range. The chip can be fine tuned to improve its performance using the calibration capabilities of the architecture. The analysis includes a comparison with another state-of-art HRPWMs showing the advantages of the proposed approach.

关键词： CMOS integrated circuits delay-line high resolution programmable delay pulse-width modulation (PWM)

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A Multiplexing DAPD Technique for Fast-Locking and Charge Pumps Calibration in PLLs

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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS 2019年第8期29卷 535-537页

作者： Liu, Shubin Sun, Depeng Ding, Ruixue Huang, Sheng Zhu, Zhangming Xidian Univ Sch Microelect Shaanxi Key Lab Integrated Circuits & Syst Xian 710071 Peoples R China

This letter presents a 5-GHz phase-locked loop (PLL) with fast-locking and charge pump (CP) calibration. Based on dual-mode time division multiplexing discriminator-aided phase detector (DAPD), the fast-locking and CP calibration procedure are proposed in a compatible and efficient manner. The proposed dual-mode time division multiplexing DAPD has coarse-resolution and fine-resolution modes, which is used in fast locking and CP calibration, respectively. The proposed technique is incorporated in a design of 5-GHz PLL. Implemented in the 0.18-mu m 1P6M CMOS process, the power dissipation is less than 18.3 mW. The measured total settling time (including fast-locking and CP calibration) is 22 mu s, evidently improved by 36 mu s over the conventional method. At 4.905 GHz, the phase noise measured at 1-MHz offset is -123.7 dBc/Hz, and the measured output spur levels are less than -70.44 dBc throughout the whole output frequency range.

关键词： Flash controller multiplexing discriminator-aided phase detector (DAPD) phase error compensation phase-locked loops (PLLs) programmable delay

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All-Digital High-Resolution PWM With a Wide Duty-Cycle Range 1

All-Digital High-Resolution PWM With a Wide Duty-Cycle Range

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Argentine Conference on Electronics (CAE)

作者： Morales, Juan I. Chierchie, Fernando Mandolesi, Pablo S. Paolini, Eduardo E. UNS CONICET Dept Ing Elect & Comp Inst Invest Ing Elect IIIE Alfredo Desages Bahia Blanca Buenos Aires Argentina CIC Prov Buenos Aires La Plata Buenos Aires Argentina

ISBN: (纸本)9781728114033

An all-digital high-resolution pulse-width modulator in standard 130-nm CMOS technology is presented in this work. The architecture is based on a digitally-controlled delay element with variable time interval up to 50 ps and adjustable against process, voltage and temperature (PVT) variations. Post-layout simulation results show a linear response between the control word and delay. The PWM modulator uses several delay elements in a hybrid configuration that allows to obtain duty cycles with 18-bit resolution, without using a high-frequency internal clock while maintaining low power consumption.

关键词： Pulse-width modulation (PWM) delay-line CMOS integrated circuits high-resolution programmable delay

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Laboratory Jitter Removal Circuit for Single-bit All-Digital Frequency Synthesis 4

Laboratory Jitter Removal Circuit for Single-bit All-Digital...

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4th Panhellenic Conference on Electronics and Telecommunications (PACET)

作者： Raptakis, Adam Oustoglou, Costas Sotiriadis, Paul P. Natl Tech Univ Athens Dept Elect & Comp Engn Athens Greece

ISBN: (纸本)9781538622889;9781538622872

All-digital frequency synthesizers based on sigma delta modulation with single-bit output can have exceptionally high dynamic range and spurs-free dynamic range, in simulation. The performance of their FPGA implementations however is significantly limited by the jitter introduced by the FPGA and its clock reference, which is translated to phase noise. This paper introduces a laboratory circuit architecture for suppressing the FPGA and reference jitter in order to achieve spectrally cleaner single-bit output sequences and demonstrate the achievable performance of the all-digital frequency synthesizers. The proposed architecture is based on a 1-Bit DAC re-clocking the single bit digital output of the FPGA using one of the two low-jitter clocks generated by a low phase noise reference oscillator. The second clock is used to clock the FPGA after passing through a programmable delay line and a small-value frequency divider. The implementation of the circuit's architecture is presented discussing the design challenges. Phase noise measurements demonstrate the performance of the circuit. Spectral measurements illustrate the effectiveness of jitter removal in the case of a sigma-delta modulator single-bit output.

关键词： Single-bit all-digital frequency synthesis sigma delta DAC phase noise jitter attenuation reclocking clock generation programmable delay

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Nonvolatile Online CMOS Trimming with Magnetic Tunnel Junctions

Nonvolatile Online CMOS Trimming with Magnetic Tunnel Juncti...

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IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

作者： Dutta, Sumit Price, Michael Baldo, Marc A. MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA

ISBN: (纸本)9781450343305

We design a programmable output delay for digital circuits, making use of the nonvolatile bit storage in magnetic tunnel junctions (MTJs), which are available in hybrid processes with CMOS. We introduce our programmable clock buffers in VLSI dot product and fast Fourier transform (FFT) circuits at the 45 nm node. We reduce the FFT clock skew by 39%. These performance improvements and the ability to reduce timing violations come at less than a 1% increase in area and power.

关键词： trimmer nonvolatile MTJ STT-MRAM timing analysis clock skew programmable delay

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Generalmanual 000064877

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2016年

Generalmanual 000064877 by published by

关键词： adjusts analog analog echo delay delay modeler delay time digital dynamic delay echo generalmanual loop loop sampler mod programmable delay rhythmic delay sampler second loop tape echo tube echo tweak tweez

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Compact lowpass filter with wide stopband using stepped impedance hairpin units

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ELECTRONICS LETTERS 2015年第1期51卷 67-U87页

作者： Liu, Shuai Xu, Jun Xu, Zhitao Univ Elect Sci & Technol China Sch Phys Elect Chengdu 610054 Peoples R China

A novel microstrip lowpass filter (LPF) with a wide stopband is presented. The basic resonator is composed of two stepped impedance hairpin units with one embedded in another, which can obtain two more transmission zeros and extend a wide stopband. Based on the proposed resonator, a demonstration LPF of compact size, sharp transition and wide stopband has been designed, fabricated and measured. The proposed filter exhibits a small size of 0.081 lambda g x 0.113 lambda g, where lambda g is the waveguide length at the cutoff frequency of 1.6 GHz. Results show good agreement with simulations and the 20 dB rejection stopband can be extended to more than 15 GHz.

关键词： frequency dividers CMOS integrated circuits injection locked oscillators two-dimensional oscillator array-based injection-locked frequency divider total delay oscillator core programmable delay programmable division ratios injection-locked divider divide-by-4-5 prescaler size 0 18 mum frequency 6 2 GHz power 0 5 mW voltage 1 8 V

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