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A pulse-coupled neural network simulator using a programmable gate array technique

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2003年第5期E86D卷 872-881页

作者： Katayama, K Iwata, A Hiroshima Univ Grad Sch Engn Hiroshima 7398527 Japan Hiroshima Univ Grad Sch Adv Sci Matter Hiroshima 7398527 Japan

In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 x 32 network connections, is designed on a chip (4.73 mm x 4.73 mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.

关键词： pulse-coupled neural network phase-locked loops dendritic tree programmable gate array reconfigurable network

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Design of Logic Module Based on Magnetic-Tunnel-Junction Elements for Nonvolatile Field-programmable gate array

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JAPANESE JOURNAL OF APPLIED PHYSICS 2009年第4期48卷 04C197-04C197页

作者： Lee, Hyunjoo Kim, Sojeong Lee, Seungyeon Lee, Seungjun Shin, Hyungsoon Ewha Womans Univ Dept Elect Engn Seoul 120750 South Korea

Magnetologic using a magnetic-tunnel-junction (MTJ) element is a very hopeful candidate for universal logic technology because it can be used to build both logic circuits and nonvolatile memories. A structure of single-layer (SL) MTJ with a novel current driver previously presented by the authors improved both functional flexibility and uniformity of magnetologic. In this paper, the design of a nonvolatile logic module using SL MTJ is presented, which can be used as a basic logic cell for nonvolatile field-programmable gate arrays (FPGAs). The S-module is a basic logic cell for Act3 family of FPGAs by Actel, which can implement arbitrary five-input logic functions. We designed an S-module using SL MTJ elements such that it can work as a programmable logic module with nonvolatility. The functional verification has been carried out by HSPICE simulator on the basis of a macro-model of SL MTJ. (C) 2009 The Japan Society of Applied Physics

关键词： MTJ SL FPGAs Magnetic tunnel junction nonvolatile Formal logic macro model Field programmable gate arrays logic cell Selective laser sintering programmable gate array Logic circuits Logic functions

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DEVELOPMENT OF A FAST TIME-TO-DIGITAL CONVERTER USING A programmable gate array

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 1995年第2-3期357卷 535-539页

作者： MINE, S TOKUSHUKU, K YAMADA, S INS University of Tokyo Japan

A fast time-to-digital converter with a 5 ns step was designed and tested by utilizing a user-programmable gate array. The stabilities against temperature and supply voltage variation were measured. A module was built with this TDC, and was successfully used in the first-level trigger system of the ZEUS detector to reject proton-beam induced background events.

关键词： proton beam programmable Logic arrays Transcranial Direct Current Stimulation programmable gate array voltage variation Converters gates arrays

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Single-Event Characterization of the 20 nm Xilinx Kintex UltraScale Field-programmable gate array under Heavy Ion Irradiation

Single-Event Characterization of the 20 nm Xilinx Kintex Ult...

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IEEE Radiation Effects Data Workshop (REDW)

作者： Lee, David S. Allen, Gregory R. Swift, Gary Cannon, Matthew Wirthlin, Michael George, Jeffrey S. Koga, Rokutaro Huey, Kangsen Sandia Natl Labs Albuquerque NM 87123 USA NASA Jet Prop Lab Pasadena CA 91109 USA Swift Engn & Radiat Serv LLC San Jose CA 95124 USA Brigham Young Univ Dept Elect & Comp Engn Ctr High Performance Reconfigurable Comp Provo UT 84602 USA Aerosp Corp El Segundo CA 90245 USA Xilinx Inc San Jose CA 95124 USA

This study examines the single-event response of the Xilinx 20 nm Kintex UltraScale Field-programmable gate array irradiated with heavy ions. Results for single-event latchup and single- event upset on configuration S... 详细信息

ISBN: (纸本)9781467376419

关键词： ion irradiation Field programmable gate arrays heavy ions programmable gate array Single event upsets Irradiation Newton meter latchlocks Single shot characterization CCDC26 gene random access machine FAM103A1 gene

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Real-time correlating autotracker realized with FPGA (Field programmable gate array)

Real-time correlating autotracker realized with FPGA (Field ...

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Conference on Applications of Digital Image Processing XX

作者： AnJun, P JiangTao, W ZhenFu, Z Beijing Inst. of Environ. features 100854 Beijing P.O.Box 142-207 China

ISBN: (纸本)0819425869

This paper describes a real-time correlation tracker realized with Field programmable gate array(FPGA). Primarily a method for correlation tracking target has been developed. The main point of this method is to present the reference pattern updating methods we implemented. Then, information on system hardware is given. The correlation tracking circuit is realized by FPGA so autotracker is small, low cost, and it could be used for real time application. Subsequently, system software can be found. System operation is controlled by high speed Digital Signal Processor(DSP) TMS320C30. In the end, the results of field-tests with our real-time correlation autotracker show that under complex background and foreground, such as clouds, trees, gasses, our approach can track a flying plane or a moving vehicle steadily.

关键词： correlation matching tracker image process programmable gate array real time pattern

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AN EXELFS MULTISCALER DMA INTERFACE FOR THE IBM PC-AT USING programmable gate arrayS

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1990年第6期37卷 2191-2197页

作者： HOVANDER, B BOHM, C Department of Physics University of Stockholm Stockholm Sweden

An IBM PC-AT interface for data acquisition from diode arrays is described. It was developed for use in an extended energy loss fine structure (EXELFS) spectrometer, where sometimes two diode arrays (containing EXELFS and low-loss spectra) need simultaneous scanning. The system operates as a multiscaler, allowing two processes to be recorded at the same time. The interface was designed using a programmable gate array (an 1800 gate-equivalent logic cell array from XILINX) to implement most of the digital circuitry and a 12-b ADC to sample the analog inputs. A 12-b DAC was used for analog outputs and for diagnostic testing purposes. The interface hardware was given a general design so that it could be used in other similar applications.

关键词： Hardware Interface energy losses overall design diodes analog output Interfaces logic cell programmable gate array diode array LOSS SPECTRA Interface

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Design of a Tritium-In-Air Monitor Using Field-programmable gate arrays

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JOURNAL OF NUCLEAR ENGINEERING AND RADIATION SCIENCE 2016年第4期2卷 044506-1-044506-3页

作者： McNelles, Phillip Lu, Lixuan Univ Ontario Inst Technol ASME 2000 Simcoe St North Oshawa ON L1H 7K4 Canada Univ Ontario Inst Technol 2000 Simcoe St North Oshawa ON L1H 7K4 Canada

Field-programmable gate arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field including instrumentation and control (I&C) systems, pulse measurement systems, particle detectors, and health physics. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to increased production of tritium, which poses a health risk and must be monitored by tritium-in-air monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of carbon-14 and the addition of noble-gas compensation, are incorporated into a new FPGA-based TAM along with the standard functions included in the original microprocessor-based TAM. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. Potential issues caused by radiation interactions with the FPGA are beyond the scope of this work.

关键词： programmable gate array Health hazards Field programmable gate arrays tritium C-14 Health physics criterion function Radiation Interaction Particle detectors laboratory procedure pulse measurement moderators updated design MONITOR

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ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2000年第4期8卷 392-400页

作者： Huang, JD Jou, JY Shen, WZ Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan

In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based held programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can efficiently provide a complete set of mapping solutions from the area-optimized one to the performance-optimize one for the given design. Furthermore, these two extreme solutions produced by our algorithm outperform the results provided by most existing algorithms. Therefore, our algorithm is very useful for the timing-driven, LUT-based FPGA synthesis.

关键词： critical-path performance tradeoffs programmable gate array technology mapping

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Automatic target recognition with dynamic reconfiguration

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JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2000年第1期25卷 39-53页

作者： Jean, J Liang, XJ Drozd, B Tomko, K Wang, Y Wright State Univ Dept Comp Sci & Engn Dayton OH 45435 USA

This paper describes the acceleration of an infrared automatic target recognition (IR ATR) application with a co-processor board that contains multiple field programmable gate array (FPGA) chips. Template and pixel level parallelism is exploited in an FPGA design for the bottleneck portion of the application. The implementation of this design achieved a speedup of 21 compared to running on the host processor. The paper then describes an FPGA resource manager (RM) developed to support concurrent applications sharing the FPGA board. With the RM, the system is dynamically reconfigurable. That is, while part of the co-processor board is busy computing, another part can be reconfigured for other purposes. The IR ATR application was ported to work with the RM and has been shown to adapt to the amount of reconfigurable hardware that is available at the time the application is executed.

关键词： dynamic reconfiguration reconfigurable hardware SERPINA2 gene Redmouth disease Automatic target recognition programmable gate array ATR gene host processor acceleration Coprocessors Target recognition Board Speeding

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Enhanced Authentication Using Hybrid PUF with FSM for Protecting IPs of SoC FPGAs

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2019年第4期35卷 543-558页

作者： Kokila, J. Ramasubramanian, N. Natl Inst Technol Dept Comp Sci & Engn Tiruchirappalli Tamil Nadu India

A new generation of technology is harder and costlier to deliver because of the physical design limitations of the silicon chip. The minute chip alone is not only compromising the requirements of the user but also creates challenges with respect to security. Architecture for two-factor authentication is designed with low-power, area and with less- human intervention. The proposed model consists of hybrid physical unclonable functions (PUFs) and finite state machine (FSM), which is used to secure the chip and intellectual property (IP) respectively. The PUFs are most often used in recent security applications such as IP protection, IC metering, hardware signature, and obfuscation. This application needs a complex algorithm with a database which consumes more cost and time. In this paper, we have proposed an authentication model consisting of strong and weak PUF with an FSM which can be used for IoT applications. The main focus of this proposal is to authenticate hardware and software IP in circuits. The Experimental evaluation illustrates that the area and power consumed are 5% and 9%, respectively, for authenticating 26 IPs with no false acceptance ratio (FAR) and 1% false rejection ratio (FRR).

关键词： System-on-a-chip design Field programmable gate array Arbiter PUF Butterfly PUF Finite state machine Two-factor authentication Hardware security and IP protection

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