检索结果-内蒙古大学图书馆

MICROPROCESSING AND MICROPROGRAMMING 1991年第5期29卷 293-302页

作者： GUSTIN, V DOBNIKAR, A EDVARD KARDELJ UNIV FAC ELECT & COMP ENGN YU-61000 LJUBLJANA YUGOSLAVIA

The aim of this paper is to outline a new approach in the digital realization of Boolean Neural Networks. It is based on programmable gate array technology (PGA). Each cell in the gate array performs the binary addition/subtraction function. Space iteration of such digital circuit enables the calculation of all output functions of neurons in the network. The topology of the network influences the connections between neurons and therefore the connections in PGA. This approach offers definite advantages over other solutions. Regular architecture with full connectivity, modularity of completely digital circuits, and possible use of programming support are some of the most important features of the proposed digital realization.

关键词： BOOLEAN NEURAL NETWORKS programmable gate array ITERATIVE LOGIC STOCHASTIC LEARNING

来源：评论

学校读者我要写书评

暂无评论

Design and design automation of rectification logic for engineering change 05

Design and design automation of rectification logic for engi...

引用

10th Asia and South Pacific Design Automation Conference

作者： Lin, Cheng-Hung Huang, Yung-Chang Chang, Shih-Chieh Jone, Wen-Ben Natl Tsing Hua Univ CS Dept Hsinchu Taiwan

ISBN: (纸本)0780387368

In a later stage of a VLSI design, it is quite often to modify a design implementation to accommodate the new specification, design errors, or to meet design constraints. In addition to meet the design schedule for the new implementation, the reduction of the mask set have become very critical. In this paper, we propose a new method to add a programmable rectification module to reduce the mask cost and to improve the turn around time. When a modification is needed, one can program the rectification module to achieve the new implementation. The rectification module can be designed by one mask programmable gate array, or an embedded FPGA. To reduce the size needed for the rectification module, we also propose algorithms, which can intelligently select some internal signals of the old implementation to become pseudo primary inputs and primary outputs. Our experimental results are very encouraging.

关键词： electronic design automation rectification logic design logic circuits VLSI field programmable gate arrays design automation rectification logic VLSI design design implementation design errors design constraints design schedule mask set reduction programmable rectification module mask cost reduction programmable gate array embedded FPGA internal signals pseudo primary inputs primary outputs design schedule programmable gate array rectification distilling Computer-Aided Design Field programmable gate arrays design constraints design error Logic design Logic circuits

来源：评论

学校读者我要写书评

暂无评论

Mono-instruction set computer architecture on a 3D optically reconfigurable gate array

Mono-instruction set computer architecture on a 3D optically...

引用

IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)

作者： Ito, Hiroyuki Watanabe, Minoru Shizuoka Univ Hamamatsu Shizuoka 4328561 Japan

ISBN: (纸本)9781479923113;9781479923137

Currently, three-dimensional VLSI technologies are being developed. However, by increasing the number of layers of TSV or stacking layers, the production difficulty of VLSI is increased. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize high-speed dynamic reconfiguration. The ORGA consists of a holographic memory, a programmable gate array, and a laser array. An ORGA can store large amounts of circuit information inside a holographic memory. The circuit information can be programmed dynamically onto an ORGA's programmable gate array in nanosecondorder. The ORGA allows high-speed dynamic reconfiguration. If the high-speed dynamic reconfiguration can be used for the implementation of processors, then the processor performance can be increased. The implementation technique is called a mono-instruction set computer (MISC) architecture. This paper presents a demonstration result of a high-performance MISC architecture that fully exploits the high-speed programmability of an ORGA.

关键词： dynamic reconfiguration Logic arrays Computer Architecture Processor Performance programmable gate array Very large scale integration holographic storage configurability layer number Through-silicon vias Taura syndrome virus of marine penaeid shrimp NANOSECOND

来源：评论

学校读者我要写书评

暂无评论

Variable-Latency Signed Addition on FPGAs 25

Variable-Latency Signed Addition on FPGAs

引用

25th International Conference on Field programmable Logic and Applications

作者： Cilardo, Alessandro Univ Naples Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy

ISBN: (纸本)9781467381239

Variable-latency, or speculative, addition is an effective technique to implement fast adders working on very long operands. Most approaches to speculative addition are either based on the assumption that operands have equiprobable independent bits, which is rarely the case in real applications due to sign-extension, or they can handle the case of signed numbers at the price of a considerable area overhead. Furthermore, many existing approaches require ad-hoc schemes preventing the reuse of standard adders typically available as optimized library components in many technologies, most notably Field-programmable gate arrays. This paper introduces an innovative scheme for speculative addition that effectively addresses both problems, yielding fast and low-area circuits able to handle sign-extended numbers speculatively and only made of optimized carry-propagation adders based on fast carry circuitry as basic building blocks.

关键词： Field programmable gate arrays adders Fasting Electric circuits Signed Addition reaction reuse programmable gate array Handles operand basic component

来源：评论

学校读者我要写书评

暂无评论

Design of Fractional PID Control System for BLDC motor Based on FPGA 30

Design of Fractional PID Control System for BLDC motor Based...

引用

30th Chinese Control and Decision Conference (CCDC)

作者： Zhang, Fan Li, Zhuangju Beijing Univ Civil Engn & Architecture Inst Elect & Informat Engn Beijing 100044 Peoples R China

ISBN: (纸本)9781538612446

In this pape, pricision brushless DC motor control system based on field programmable gate array (FPGA) was designed. The system consists of two parts: FPGA and peripheral circuits. FPGA as the control core of the whole circuit, through the hardware programming language VerilonFIDE programming FPGA internal hardware circuit to complete fractional PID control algorithm, based on fractional PID control mode to achieve the appropriate duty cycle PWM output controller design. The simulation results show that the fractional-order PID controller based on FPGA has the advantages of simple structure, flexible control and strong anti-interference ability, meanwhile meets the actual requirements of motor speed regulation.

关键词： programmable gate array Brushless DC Motor PWM Fractional PID

来源：评论

学校读者我要写书评

暂无评论

Security enhancements for FPGA-based MPSoCs: a boot-to-runtime protection flow for an embedded Linux-based system

Security enhancements for FPGA-based MPSoCs: a boot-to-runti...

引用

7th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

作者： Cotret, Pascal Devic, Florian Gogniat, Guy Badrignans, Benoit Torres, Lionel Univ Bretagne Sud Lab Lab STICC Lorient France Univ Montpellier 2 Lab LIRMM Montpellier France Netheos Montpellier France

ISBN: (纸本)9781467325721

Nowadays, embedded systems become more and more complex: the hardware/software codesign approach is a method to create such systems in a single chip which can be based on reconfigurable technologies such as FPGAs (Field-programmable gate arrays). In such systems, data exchanges are a key point as they convey critical and confidential information and data are transmitted between several hardware modules and software layers. In case of an FPGA development life cycle, OS (Operating System) / data updates as runtime communications can be done through an insecure link: attackers can use this medium to make the system misbehave (malicious injection) or retrieve bitstream-related information (eavesdropping). Recent works propose solutions to securely boot a bitstream and the associated OS while runtime transactions are not protected. This work proposes a full boot-to-runtime protection flow of an embedded Linux kernel during boot and confidentiality/integrity protection of the external memory containing the kernel and the main application code/data. This work shows that such a solution with hardware components induces an area occupancy of 10% of a xc6vlx240t Virtex-6 FPGA while having an improved throughput for Linux booting and low-latency security for runtime protection.

关键词： hardware module BOOTS Field programmable gate arrays Confidential Information bit stream external memory Runtime programmable gate array data systems

来源：评论

学校读者我要写书评

暂无评论

Universal communication module based on AMC standard

Universal communication module based on AMC standard

引用

15th International Conference on Mixed Design of Integrated Circuits and Systems

作者： Makowski, D. Piotrowski, A. Napieralski, A. Tech Univ Lodz Dept Microelect & Comp Sci PL-90924 Lodz Poland

ISBN: (纸本)9788392263272

The linear accelerator driving Free Electron Laser in Hamburg requires a reliable and accurate Low Level Radio Frequency control system. A VME standard is currently used to design the LLRF control of the FLASH. However, the present VME-based LLRF control system has serious drawbacks concerning reliability, upgradeability and serviceability. The Advanced Telecommunication Computing Architecture (ATCA) and Advanced Mezzanine Card (AMC) standards could be more suitable for a demanding LLRF system of the XFEL accelerator. New standards offer useful features that allow enhancing the reliability and availability of the LLRF system. However, a significant number of additional features like: serial high-speed interface controllers, complex power supply units, monitoring and management systems must be implemented to take a full advantage of ATCA or AMC standards. The paper presents a universal AMC-B module that can used for a fast development of AMC-based subsystems, designed according to the AMC standard. The AMC module controlled by Xilinx FPGA, equipped with PCI Express and Rocket 10 interfaces as well as Module Management Unit can be connected to AMC-A module and therefore enables fast and easy development of AMC-based systems for accelerators and telecommunication applications.

关键词： Advanced Telecommunication Computing Architecture Advanced Mezzanine Card PCI Express field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

引用

JAPANESE JOURNAL OF APPLIED PHYSICS 2015年第9期54卷 9MA06.1-9MA06.1页

作者： Seto, Daisaku Watanabe, Minoru Shizuoka Univ Dept Elect & Elect Engn Hamamatsu Shizuoka 4328561 Japan

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 x 10(4) times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and highspeed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation. (C) 2015 The Japan Society of Applied Physics

关键词： Field programmable gate arrays Logic arrays configurability Radiation Tolerance programmable gate array holographic storage Radiation Radiation hardening

来源：评论

学校读者我要写书评

暂无评论

Digitální osciloskop na platformě FITkit

Digitální osciloskop na platformě FITkit

引用

作者： Veškrna, Ondřej Brno University of Technology

Práce se zabývá návrhem zařízení, které umožní sledovat průběh měřeného signálu na obrazovce počítače na principu digitálního osciloskopu. Řídic&... 详细信息

Práce se zabývá návrhem zařízení, které umožní sledovat průběh měřeného signálu na obrazovce počítače na principu digitálního osciloskopu. Řídicím prvkem zařízení je programovatelné hradlové pole osazené na platformě FITkit. Konfigurace hradlového pole má za úkol řídit vzorkování vstupního signálu a získané vzorky odesílat prostřednictvím USB rozhraní do počítače. Aplikace implementovaná na PC se pokusí signál rekonstruovat a výsledek zobrazí na monitoru počítače.

关键词： Platforma FITkit FPGA programovatelné hradlové pole analogově číslicový převod A/D převodník vestavěný systém mikrokontrolér MCU SPI USB rozhraní C# VHDL FITkit platform FPGA programmable gate array analog to digital conversion A/D convert

来源：评论

学校读者我要写书评

暂无评论

Big data application in exchange rate financial prediction platform based on FPGA and human -computer interaction

引用

MICROPROCESSORS AND MICROSYSTEMS 2021年 80卷 103626-103626页

作者： Huang, Ping Hunan Univ Sch Econ & Trade Changsha 410079 Hunan Peoples R China

A prediction is a statement about the financial market. The financial market prediction may lack sufficient reasons or any good stock market analysis. The financial prediction may be correct or inaccurate on any given occasion, or average, Model-based or information. The financial prediction is made by various methods, including hundreds of economic evaluation and test systems, which are Observable in the gate array. The Digital signal processing system and IoT (Internet of thing) for exchange rate finical perdition platform in the previous method. The previous method is difficulty in lower investment to reduce inflation and false value setting. The proposed method is based on programmable gate and learning for finical predication. A critical challenge of financial forecasting issues, along with opportunities that arise from the unique characteristics of financial data, signal-to-noise ratios, persistent predictors, predictive instability and environmental predictability resulting from competitive pressure and investors learning. The machine approaches for predicting the mean, variance, and probability distribution of asset returns. programmable gate array covers how to evaluate financial forecasts, which leads to data mining concerns, taking into account the possibility that numerous forecast models are being considered.

关键词： Exchange rate Financial prediction platform programmable gate array

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：