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All-Optical 2 x 2-Bit Multiplier at 40 Gb/s Based on Canonical logic Units-based programmable logic array (CLUs-PLA)

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2020年第20期38卷 5586-5594页

作者： Dong, Wenchan Lei, Lei Chen, Liao Yu, Yu Zhang, Xinliang Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Sch Opt & Elect Informat Wuhan 430074 Peoples R China Shenzhen Univ Sch Phys & Optoelect Engn Shenzhen 518060 Peoples R China

Multiplication is an important function of logic operation, and all-optical high-speed multiplication logic operation will lay the foundation for future high-speed optical computing and optical logic processing chip. In this article, by introducing the structure of canonical logic units-based programmable logic array (CLUs-PLA), we propose a scheme to realize all-optical 2 x 2-bit multiplier. In our scheme, different types of CLUs are generated using bidirectional multichannel four-wave mixing (FWM), then the results of multiplier at the operation of 40 Gb/s can be obtained by simple power coupling of corresponding CLUs. Eye diagrams of logic results are widely open, and the extinction ratios are more than 9.4 dB. Comparing with multiplier based on traditional hierarchical computing, multiplier based on parallel computing in our scheme can reduce the number of AND gate by 4, and avoid further deterioration of signal quality due to three-order cascade of AND gate. Moreover, the scheme has the potential to realize m x n-bit (m + n <= 9, m and n are positive integers) multiplier at higher operation rate in the integrated platform, paving the way towards multi-bit high-speed compact complex logic devices for future high-performance optical computing and optical logic processing chip.

关键词： High-speed optical techniques programmable logic arrays Optical mixing Optical signal processing Couplings Optical amplifiers Optical signal processing optical logic devices programmable logic array four-wave mixing

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All-Optical Canonical logic Units-Based programmable logic array (CLUs-PLA) Using Semiconductor Optical Amplifiers

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2012年第22期30卷 3532-3539页

作者： Lei, Lei Dong, Jianji Yu, Yu Tan, Sisi Zhang, Xinliang Huazhong Univ Sci & Technol Natl Lab Optoelect Wuhan 430074 Peoples R China Huazhong Univ Sci & Technol Sch Opt & Elect Informat Wuhan 430074 Peoples R China

All-optical programmable logic arrays (PLAs) based on canonical logic units (CLUs), i.e., minterms and maxterms, are presented. We experimentally demonstrated the full set of two-input and three-input minterms as well as maxterms using the cross-gain modulation in semiconductor optical amplifiers (SOAs). Maxterms can be easily obtained based on minterms. The reconfigurability and scalability of the system are largely enhanced compared to our previous work. Correct and clear temporal waveforms are achieved for all the canonical logic units. The measured extinction ratios of two-input and three-input CLUs are similar to 15dB and similar to 11 dB, respectively. Based on the CLUs, both sum-of-products and product-of-sums typed PLAs are exhibited. Six important logic functions, including full-adder, full-subtractor, multiplier, multiplexer, demultiplexer and decoder, are presented as examples to show that the canonical logic units-based programmable logic array (CLUs-PLA) can be reconfigured to perform different logic functions. The features of simple architectures, integration ability of SOA and programmable filter enable the great integration potential for CLUs-PLA.

关键词： Nonlinear optics optical computing optical logic devices optical signal processing programmable logic array semi-conductor optical amplifier

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Investigation on Expanding the Computing Capacity of Optical programmable logic array Based on Canonical logic Units

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2018年第18期36卷 3949-3958页

作者： Dong, Wenchan Hou, Jie Zhang, Xinliang Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan 430074 Hubei Peoples R China Huazhong Univ Sci & Technol Sch Opt & Elect Informat Wuhan 430074 Hubei Peoples R China

A general structure of an all-optical canonical logic based programmable logic array (CLUs-PLA) based on three methods to expand its computing capacity is presented. These methods include introducing bidirectional structure for nonlinear devices, utilizing wavelength multicast of four-wave mixing (FWM), and exploiting different nonlinear effects simultaneously, which fully utilize the parallelism of optical signals. Aiming at this general structure, we quantitatively analyze its computing capacity in detail, which is obviously enlarged comparing with the standard CLUs-PLA. To demonstrate our proposal, an experiment of CLUs' simultaneous generation in nine parallel wavelength channels using bidirectional FWM is carried out. Comparing with the standard CLUs-PLA, the computing capacity of the expanded one is enlarged to 7.5 times.

关键词： Four-wave mixing highly nonlinear fiber optical logic devices optical signal processing programmable logic array

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LOW POWER ADIABATIC programmable logic array WITH SINGLE CLOCK IAPDL

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2008年第2期17卷 211-219页

作者： Yang, W. J. Zhou, Y. Lau, K. T. Nanyang Technol Univ Ctr Integrated Circuits & Syst Sch Elect & Elect Engn Singapore 639798 Singapore

A novel implementation of a low power adiabatic PLA with a single power clock (IAPDL-SC PLA) is presented. The isolation transistor in the AND array is removed. The power clock is shared by the AND array and the OR array. In this way, the proposed PLA not only saves the device components but also reduces the power consumption. For 3V V(DD) and 200 MHz power clock frequency, the simulation results using Hspice show that the power saving is 79.48% compared to dynamic CMOS PLA, 69.34% compared to APDL PLA, and 40.40% compared to IAPDL PLA. For the 5 x 8 x 4 PLA design, the device saving is 30.77% compared to APDL PLA and 12.90% compared to IAPDL PLA. The diodes are the critical components for all the technology designs. Current simulation is based on 0.8 mu m process and the power consumption can be further reduced using the more downsized technology designs.

关键词： Low power CMOS programmable logic array adiabatic circuits single power clock

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IAPDL-based low-power adiabatic programmable logic array

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MICROELECTRONICS JOURNAL 2000年第4期31卷 235-238页

作者： Lau, KT Liu, F Nanyang Technol Univ Ctr Microelect Sch Elect & Elect Engn Singapore 639798 Singapore

A novel low power programmable logic array structure based on adiabatic switching is presented. Simulation results using HSPICE with 0.8 mu m technology designs show that the power savings of the proposed adiabatic programmable logic array (PLA) circuit is up to 60%, compared to the dynamic PLA circuit. Compared to APDL (Adiabatic Pseudo-Domino logic) PLA, the power saving is about 15% and the device count savings is about 20%. The power saving is improved further at lower supply voltages. At 2 V Vdd and 200 MHz clock frequency, the power saving is about 25% compared to APDL PLA. Compared to static PLA, the power saving is even more significant. HSPICE simulations also show that the proposed PLA can function correctly up to I GHz at 5 V Vdd, and the supply voltage can be scaled down to 2 V at 200 MHz. (C) 2000 Elsevier Science Ltd. All rights reserved.

关键词： adiabatic pseudo-domino logic programmable logic array HSPICE

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A Novel Test Structure to Implement a programmable logic array Using Split-Gate Flash Memory Cells

A Novel Test Structure to Implement a Programmable Logic Arr...

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26th IEEE International Conference on Microelectronic Test Structures (ICMTS)

作者： Om'mani, Henry Tadayoni, Mandana Thota, Nitya Yue, Ian Do, Nhan Silicon Storage Technol San Jose CA 95134 USA

ISBN: (纸本)9781467348485;9781467348454

We developed a novel configurable logic array test structure using a highly scalable 3rd generation split-gate flash memory cell that features low power and fast configuration time. This split-gate SuperFlash (R) configuration element (SCE) has been demonstrated with a 90nm embedded Flash technology. The resulting SCE eliminates the need for esoteric fabrication process, and sensing, and SRAM circuits and reduces configuration time for programmable arrays (PA) such as FPGAs and CPLDs. Additionally, SCE inherently ports the advantages of SST's split-gate Flash memory technology with compact area, low-voltage read operation, low-power poly-to-poly erase and source-side channel hot electron (SSCHE) injection programming mechanisms, along with superior reliability.

关键词： Index CPLD FPGA programmable logic array Split-Gate Flash Memory

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Parallel all-optical programmable logic array based on multichannel four-wave mixing 10

Parallel all-optical programmable logic array based on multi...

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Conference on Optoelectronic Devices and Integration X

作者： Dong, Wenchan Gu, Wentao Gao, Xiaoyan Zhang, Xinliang Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan 430074 Peoples R China Huazhong Univ Sci & Technol Sch Opt & Elect Informat Wuhan 430074 Peoples R China

ISBN: (数字)9781510646384

ISBN: (纸本)9781510646384;9781510646377

Canonical logic units-based programmable logic array (CLUs-PLA) is an important combinational logic device for its flexibility and user-defined feature. All-optical high-speed CLUs-PLA will lay the foundation for future high-speed optical computing and optical logic processing chip. For standard three-input all-optical CLUs-PLA, one nonlinear device can produce only one type of three-input CLU. In this paper, we propose and experimentally demonstrate a scheme that one nonlinear device can produce eight different types of three-input CLUs simultaneously, owing to introducing bidirectional four-wave mixing and wavelength spacing optimization. We obtain error-free performance for all three-input CLUs operations at 40 Gb/s. Comparing to standard three-input all-optical CLUs-PLA, parallel all-optical CLUs-PLA based on our proposed scheme can greatly reduce the number of nonlinear devices and simplify the computing system.

关键词： Optical signal processing programmable logic array optical logic devices four-wave mixing highly nonlinear fiber

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100 Gb/s All-Optical programmable logic array Chip Based on Full Set of Canonical logic Units

100 Gb/s All-Optical Programmable Logic Array Chip Based on ...

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2023 Asia Communications and Photonics Conference/2023 International Photonics and Optoelectronics Meetings, ACP/POEM 2023

作者： Gao, Xiaoyan Gu, Wentao Dong, Wenchan Xu, Jing Dong, Jianji Zhang, Xinliang Huazhong University of Science and Technology Wuhan National Laboratory for Optoelectronics Wuhan China Huazhong University of Science and Technology School of Optical and Electronic Information Wuhan China

We experimentally demonstrate an all-optical programmable logic array scheme through linear pre-coding and nonlinear four-wave mixing in silicon-based integrated chip. The full set of canonical logic units are generat... 详细信息

ISBN: (纸本)9798350312614

关键词： all-optical signal processing optical computing programmable logic array silicon photonics

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Large-scale optical programmable logic array for two-dimensional cellular automaton

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Advanced Photonics 2024年第5期6卷 104-113页

作者： Wenkai Zhang Bo Wu Wentao Gu Junwei Cheng Hailong Zhou Dongmei Huang Ping-kong Alexander Wai Liao Chen Wenchan Dong Jianji Dong Xinliang Zhang Huazhong University of Science and Technology Wuhan National Laboratory for OptoelectronicsSchool of Optical and Electronic InformationWuhanChina The Hong Kong Polytechnic University Shenzhen Research Institute ShenzhenChina The Hong Kong Polytechnic University Photonics Research InstituteDepartment of Electrical and Electronic EngineeringHong KongChina Hong Kong Baptist University Department of PhysicsHong KongChina

Despite more than 40 years of development,it remains difficult for optical logic computing to support more than four operands because the high parallelism of light has not been fully exploited in current methods that are restrained by inefficient optical nonlinearity and redundant input *** this paper,we propose a large-scale optical programmable logic array(PLA)based on parallel spectrum *** fully exploiting the wavelength resource,an eight-input PLA is experimentally demonstrated with 256 wavelength *** it is extended to nine-input PLA through the combination of wavelength’s and spatial *** on PLA,many advanced logic functions like 8-256 decoder,4-bit comparator,adder and multiplier,and state machines are first realized in *** implement the two-dimensional optical cellular automaton(CA)for what we believe is the first time and run Conway’s Game of Life to simulate the complex evolutionary processes(pulsar explosion,glider gun,and breeder).Other CA models,such as the replicator-like evolution and the nonisotropic evolution to generate the Sierpinski triangle are also *** work significantly alleviates the challenge of scalability in optical logic devices and provides a universal optical computing platform for two-dimensional CA.

关键词： optical computing programmable logic array optical cellular automaton

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Fault-tolerant programmable logic array for nanoelectronics

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2012年第12期40卷 1233-1247页

作者： Flak, Jacek Laiho, Mika VTT VTT Tech Res Ctr Finland FIN-02044 Espoo Finland Univ Turku Microelect Lab FIN-20520 Turku Finland

This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single-electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies. Copyright (c) 2012 John Wiley & Sons, Ltd.

关键词： nanoelectronics programmable logic array fault tolerance hybrid circuits single-electron devices

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