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INPUT VARIABLE ASSIGNMENT AND OUTPUT PHASE OPTIMIZATION OF PLAS

IEEE TRANSACTIONS ON COMPUTERS 1984年第10期33卷 879-894页

作者： SASAO, T IBM CORP THOMAS J WATSON RES CTRYORKTOWN HTSNY 10598

A PLA minimization system having the following features is presented: 1) minimization of both two-level PLA"s and PLA"s with two-bit decoders; 2) optimal input variable assignment to the decoders; 3) optimal output phase assignment; and 4) essential prime implicants detection without generating all the prime implicants.

关键词： Adder complexity of logic circuits decoder assignment essential prime implicants logic design output phase optimization programmable logic array switching theory

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3-STEP HEURISTIC ALGORITHM FOR OPTIMAL PLA COLUMN FOLDING

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ELECTRONICS LETTERS 1988年第17期24卷 1088-1090页

作者： YANG, YY KYUNG, CM Department of Electrical Engineering Korea Advanced Institute of Science & Technology Seoul Korea

A three-step heuristic algorithm for PLA column folding is presented, which is significantly faster than the earlier works and provides nearly optimal results. The three steps are (i) Min-Cut partition of vertices in the column intersection graph, (ii) determination of product order using Fiduccia's Min-Net Cut algorithm, and (iii) head-tail pairing for deciding column folding pairs.

关键词： column intersection graph logic circuits three-step heuristic algorithm integrated logic circuits PLA column folding logic design graph theory cellular arrays min-cut partition programmable logic array logic design methods min-net cut algorithm Combinatorial mathematics column folding pairs head-tail pairing Network topology fast near optimal algorithm

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AREA-OPTIMIZED REGISTERS USING A FOLDED PLA

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IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS 1990年第1期137卷 28-32页

作者： HUERTAS, JL QUINTANA, JM AVEDILLO, MJ Departamento de Electrónica y Electromagnetismo Facultad de Fisica Universidad de Sevilla Avda. Reina Mercedes s/n Sevilla 41012 Spain

A method for implementing flip-flops using a folded PLA in a feedback connection is proposed. The new approach is shown to give effective circuits in terms of silicon area.

关键词： programmable logic array logic design circuit layout flip-flops cellular arrays shift registers integrated logic circuits finite state machine synthesis regular array folding chip area-reduction feedback connection folded PLA logic arrays Digital circuits

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CONCURRENT ERROR-DETECTION AND TESTING FOR LARGE PLAS

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IEEE TRANSACTIONS ON ELECTRON DEVICES 1982年第4期29卷 756-764页

作者： KHAKBAZ, J MCCLUSKEY, EJ STANFORD UNIV DEPT COMP SCICTR RELIABLE COMPCOMP SYST LABSTANFORDCA 94305

A system of checkers is designed for concurrent error detection in large PLA's. This system combines concurrent error detection with off-line functional, testing of the PLA by using the same checker hardware for both purposes. The result is a significant saving in hardware cost. For a case example, the total hardware cost is estimated at about 37 percent of the original PLA area. The system is almost totally self-checking and, although the test patterns are not function-independent, their generation algorithm is simple. The total test time for the entire system is within the range of that of some recent PLA design schemes which were specifically aimed at simplifying off-line testing, but which have no provisions for concurrent error detection.

关键词： 1-out-of-n code checker concurrent error detection nonconcurrent PLA PLA programmable logic array testing two-rail code checker

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DESIGN AND APPLICATION OF SELF-TESTING COMPARATORS IMPLEMENTED WITH MOS PLAS

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IEEE TRANSACTIONS ON COMPUTERS 1984年第6期33卷 493-506页

作者： TAMIR, Y SEQUIN, CH Computer Science Division Department of Electrical Engineering and Computer Sciences University of California

A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attractive. A critical circuit in this context is a self-testing comparator. Faults in the comparator must be detected so that they do not mask discrepancies between the duplicated modules.

关键词： Concurrent error detection MOS PLA fault model duplication and matching faults in VLSI circuits programmable logic array self-testing comparator two-rail code checker

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PLA-Based regular structures and their synthesis

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2003年第6期22卷 723-729页

作者： Mo, F Brayton, R Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

Two regular circuit structures based on the programmable logic array (PLA) are proposed. They provide alternatives to the widely used standard-cell structure and have better predictability and simpler design methodologies. A whirlpool PLA is a cyclic four-level structure, which has a compact layout. Doppio-ESPRESSO, a four-level logic minimization algorithm, is developed for the synthesis of Whirlpool PLAs. A river PLA is a stack of multiple output PLAs, which uses river routing for the interconnections of the adjacent PLAs. A synthesis algorithm for river PLAs uses multilevel logic synthesis, simulated-annealing, and ESPRESSO targeting a combination of minimal area and delay.

关键词： programmable logic array

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Ultra-Low Power Neuromorphic Computing With Spin-Torque Devices

Ultra-Low Power Neuromorphic Computing With Spin-Torque Devi...

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3rd Berkeley Symposium on Energy Efficient Electronic Systems (E3S)

作者： Sharad, Mrigank Fan, Deliang Yogendra, Karthik Roy, Kaushik Purdue Univ Dept Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781479933723

Emerging spin transfer torque (ST) devices such as lateral spin valves and domain wall magnets may lead to ultralow- voltage, current-mode, spin-torque switches that can offer attractive computing capabilities, beyond digital switches. This paper reviews our work on ST-based non-Boolean data-processing applications, like neural-networks, which involve analog processing. Integration of such spin-torque devices with charge-based devices like CMOS can lead to highly energy-efficient information processing hardware for applicatons like pattern-matching, neuromorphic-computing, image-processing and data-conversion. Simulation results for analog image processing and associative computing has shown the possibility of similar to 100X improvement in energy efficiency as compared to a 15nm CMOS ASIC.

关键词： spin logic low power threshold logic analog neural networks non-Boolean programmable logic array interconnect

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Waveform Digitization with programmable Windowed Real-Time Trigger Capability

Waveform Digitization with Programmable Windowed Real-Time T...

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IEEE Nuclear Science Symposium Conference 2009

作者： Huang, Wei Chiang, Shiuh-hua Wood Kleinfelder, Stuart Univ Calif Irvine Irvine CA 92697 USA

ISBN: (纸本)9781424439614

A transient waveform digitizer circuit with continuous sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 mu m CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample storage, and attains 2 GHz sample speeds with up to 2 GHz analog bandwidth. Sample clock generation adopts a semi-synchronous approach, combining a phase-locked loop for highspeed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sample voltage levels are compared against reference levels that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample wide windows against up to 72 programmable patterns in real-time using a programmable logic array. Each trigger window is 8 samples-wide, overlapped sample by sample in a circular fashion through the entire 128 sample array. A trigger is flagged within 7 ns if there is a match, after which on-chip digitization can proceed via 128 parallel 10-bit converters.

关键词： Transient digitizer sample and hold analog to digital conversion programmable logic array phase-locked loop

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Two-Level logic minimization for low power

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ACM Transactions on Design Automation of Electronic Systems 1999年第1期4卷 52-69页

作者： Itri, Jyh-Mou Tseng Jou, Jing-Yang ITRI Taiwan National Chiao Tung University Taiwan Computer and Communication Research Lab. ITRI Bldg. 14 Chutung Hsinchu 310 195-11 Sec. 4 Chung Hsing Rd Taiwan Department of Electronics Engineering National Chiao Tung University Hsinchu 300 1001 Ta-Hsueh Road Taiwan

In this paper we present a complete Boolean method for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates, and dynamic PLA implementations. We modify the espresso algorithm by adding our heuristics, which bias logic minimization toward lowering power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. The experimental results are promising. © 1999 ACM.

关键词： logic synthesis Low power design programmable logic array Two-level logic minimization

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Controllable Current and Voltage Power sources using FPGA

Controllable Current and Voltage Power sources using FPGA

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11th IFAC/IEEE International Conference on programmable Devices and Embedded Systems (PDeS)

作者： Koucky, Vaclav Lahoda, Jiri Petrankova, Zuzana Univ W Bohemia Dept Appl Elect & Telecommun Plzen 30614 Czech Republic

ISBN: (纸本)9783902823144

This paper deals with the development and design of digitally controllable, three-phase current and voltage power sources. The main, digitally controlled parameters of the power source are frequency, phase-shift and amplitudes of two separate sine-wave systems. Possibilities and means of implementation are discussed and a verified solution is described. The reason why this development was done is the lack of power sources on the market. The three-phase voltage and the tree-phase current systems are isolated by power transformers. Among many possibilities of voltage and current control, the method based on direct digital synthesis was selected. Control circuits of the power sources are described in VHDL and implemented in an FPGA device.

关键词： VHDL programmable logic array FPGA voltage source current source direct digital synthesis DDS

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