This paper first discusses the symmetric property of the minimal covering problem in terms of group theory and then the use of this property in the branch-and-bound method for solving the problem. Computational result...
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This paper first discusses the symmetric property of the minimal covering problem in terms of group theory and then the use of this property in the branch-and-bound method for solving the problem. Computational results on solving sample problems are shown to demonstrate the improvement of computational efficiency of the branch-and-bound method by the utilization of the symmetric property. The sample problems contain the minimal sum derivation of symmetric switching functions, as an application to the design of minimal programmable logic arrays (PLA"s). It is shown that when the minimal covering problem derived for the given switching function has symmetric permutations, the given switching function may not be symmetric; although when the given switching function is symmetric, the minimum covering problem obtained from the function is symmetric. The branch-and-bound method based on the symmetric property can be applied not only to symmetric switching functions but also to switching functions which are not symmetric, if the corresponding minimal covering problems have symmetric permutations. The method can be also applied to minimal covering problems which arise outside the minimal sum derivation problems for switching functions.
作者:
SASAO, TDepartment of Electronic Engineering
Osaka University Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions
A recursive algorithm to obtain a complement of a sum-of-products expression for a binary function with p-valued inputs is presented. It produces at most pn/2 products for n-variable functions, whereas a conventional ...
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A recursive algorithm to obtain a complement of a sum-of-products expression for a binary function with p-valued inputs is presented. It produces at most pn/2 products for n-variable functions, whereas a conventional elementary algorithm produces O(tn·n(1-t)/2) products where t = 2P -1. It is 10-20 times faster than the elementary one when p = 2 and n = 8. For large practical-problems, it produces many fewer products than the disjoint sharp algorithm used by MINI. Appplications of the algorithm to PLA minimization are also presented.
A new design of testable PLA"s is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it ha...
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A new design of testable PLA"s is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA"s. This design, however, is not appropriate for built-in test.
作者:
SASAO, TIBM CORP
THOMAS J WATSON RES CTRYORKTOWN HTSNY 10598
A PLA minimization system having the following features is presented: 1) minimization of both two-level PLA"s and PLA"s with two-bit decoders; 2) optimal input variable assignment to the decoders; 3) optimal...
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A PLA minimization system having the following features is presented: 1) minimization of both two-level PLA"s and PLA"s with two-bit decoders; 2) optimal input variable assignment to the decoders; 3) optimal output phase assignment; and 4) essential prime implicants detection without generating all the prime implicants.
A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attra...
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A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attractive. A critical circuit in this context is a self-testing comparator. Faults in the comparator must be detected so that they do not mask discrepancies between the duplicated modules.
It has been shown that small PLAs can be made self-testing. The proposed methods however fail to handle large functions fast or result in a large overhead. Here a method is shown that can be implemented efficiently at...
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The work contains the design of the fail-safe system with the redundancy. The elimination of influence of the common mode failures is achieved by the application of two mutually complementary units which are either th...
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The work contains the design of the fail-safe system with the redundancy. The elimination of influence of the common mode failures is achieved by the application of two mutually complementary units which are either the asynchronous machines or the sequential microcomputers. This two copies use the different codes.
A system of checkers is designed for concurrent error detection in large PLA's. This system combines concurrent error detection with off-line functional, testing of the PLA by using the same checker hardware for b...
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A system of checkers is designed for concurrent error detection in large PLA's. This system combines concurrent error detection with off-line functional, testing of the PLA by using the same checker hardware for both purposes. The result is a significant saving in hardware cost. For a case example, the total hardware cost is estimated at about 37 percent of the original PLA area. The system is almost totally self-checking and, although the test patterns are not function-independent, their generation algorithm is simple. The total test time for the entire system is within the range of that of some recent PLA design schemes which were specifically aimed at simplifying off-line testing, but which have no provisions for concurrent error detection.
The design of integrated cLrcuJts to Implement arbitrary regular expressions is considered In general, a regular expression with n operands may be converted into a nondetermmlstlc fimte automaton with at most n states...
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作者:
SASAO, TDepartment of Electrical Engineering
Osaka University Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions
Generalized Boolean functions are shown to be useful for the design of programmable logic arrays (PLA"s), and the complexity of three types of PLA"s is obtained by the theory of multiple- valued decompositio...
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Generalized Boolean functions are shown to be useful for the design of programmable logic arrays (PLA"s), and the complexity of three types of PLA"s is obtained by the theory of multiple- valued decomposition. A two-level PLA consists of an AND array and an OR array, and they are cascaded to perform a two-level AND-OR circuit. A PLA with decoders consists of decoders, an AND array, and an OR array. A three-level PLA consists of a D array, an AND array, and an OR array, and they are cascaded to perform a three-level OR- AND-OR circuit. It is shown that a generalized Boolean function f(X1, X2,··, Xr):X Bni → B, where B = {0,1}, is represented by a generalized Boolean expression of 2ni-valued variables Xi; and f can be directly realized by a PLA with decoders or a three-level PLA. To realize a function of n-variables (n = 2r), the following sizes are shown to be sufficient: for a two-level PLA, (n + ½) 2n; for a PLA with two-bit decoders, 4(n + 4) 2n; for a three-level PLA, 2n+ (3n + l)√2n+ 2n2Especially in the case of PLA with two-bit decoders, the following sizes are shown to be necessary and sufficient: for an arbitrary symmetric function, 3/2(n + ½) √3n; and for a parity function, (n + ½)√ 2n.
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