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32nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

作者： Roy, Kaushik Sharad, Mrigank Fan, Deliang Yogendra, Karthik Purdue Univ Dept Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781479910717

In this paper we discuss the potential of emerging spin-torque devices for computing applications. Recent proposals for spin-based computing schemes may be differentiated as 'all-spin' vs. hybrid, programmable vs. fixed, and, Boolean vs. non-Boolean. All-spin logic-styles may offer high area-density due to small form-factor of nano-magnetic devices. However, circuit and system-level design techniques need to be explored that leaverage the specific spin-device characterisitcs to achieve energy-efficiency, performance and reliability comparable to those of CMOS. The non-volatility of nano-magnets can be exploited in the design of energy and area-efficient programmable logic. In such logic-styles, spin-devices may play the dual-role of computing as well as memory-elements that provide field-programmability. Spin-based threshold logic design is presented as an example. Emerging spintronic phenomena may lead to ultra-low-voltage, current-mode, spin-torque switches that can offer attractive computing capabilities, beyond digital switches. Such devices may be suitable for non-Boolean data-processing applications which involve analog processing. Integration of such spin-torque devices with charge-based devices like CMOS and resistive memory can lead to highly energy-efficient information processing hardware for applicatons like pattern-matching, neuromorphic-computing, image-processing and data-conversion. Towards the end, we discuss the possibility of applying emerging spin-torque switches in the design of energy-efficient global interconnects, for future chip multiprocessors.

关键词： spin logic low power threshold logic analog neural networks non-Boolean programmable logic array interconnect

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PLA-Based regular structures and their synthesis

PLA-Based regular structures and their synthesis

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International Workshop on logic and Synthesis (IWLS)

作者： Mo, F Brayton, R Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

Two regular circuit structures based on the programmable logic array (PLA) are proposed. They provide alternatives to the widely used standard-cell structure and have better predictability and simpler design methodologies. A whirlpool PLA is a cyclic four-level structure, which has a compact layout. Doppio-ESPRESSO, a four-level logic minimization algorithm, is developed for the synthesis of Whirlpool PLAs. A river PLA is a stack of multiple output PLAs, which uses river routing for the interconnections of the adjacent PLAs. A synthesis algorithm for river PLAs uses multilevel logic synthesis, simulated-annealing, and ESPRESSO targeting a combination of minimal area and delay.

关键词： programmable logic array

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Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives

Computing with Spin-Transfer-Torque Devices: Prospects and P...

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IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Roy, Kaushik Sharad, Mrigank Fan, Deliang Yogendra, Karthik Purdue Univ Dept Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781479937653

In this paper we discuss the potential of emerging spin-torque devices for computing applications. Recent proposals for spin-based computing schemes may be differentiated as 'all-spin' vs. hybrid, programmable vs. fixed, and, Boolean vs. non-Boolean. All-spin logic-styles may offer high area-density due to small form-factor of nano-magnetic devices. However, circuit and system-level design techniques need to be explored that leaverage the specific spin-device characterisitcs to achieve energy-efficiency, performance and reliability comparable to those of CMOS. The non-volatility of nano-magnets can be exploited in the design of energy and area-efficient programmable logic. In such logic-styles, spin-devices may play the dual-role of computing as well as memory-elements that provide field-programmability. Spin-based threshold logic design is presented as an example. Emerging spintronic phenomena may lead to ultra-low-voltage, current-mode, spin-torque switches that can offer attractive computing capabilities, beyond digital switches. Such devices may be suitable for non-Boolean data-processing applications which involve analog processing leading to highly energy-efficient information processing hardware for applicatons like patternmatching, neuromorphic-computing, image-processing and data-conversion. Towards the end, we discuss the possibility of applying emerging spin-torque switches in the design of energy-efficient global interconnects, for future chip multiprocessors.

关键词： spin logic low power threshold logic analog neural networks non-Boolean programmable logic array interconnect

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Brain-Inspired Computing with Spin Torque Devices

Brain-Inspired Computing with Spin Torque Devices

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Roy, Kaushik Sharad, Mrigank Fan, Deliang Yogendra, Karthik Purdue Univ Dept Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9783981537024

In this paper we discuss the potential of emerging spintorque devices for computing applications. Recent proposals for spin-based computing schemes may be differentiated as 'all-spin' vs. hybrid, programmable vs. fixed, and, Boolean vs. non-Boolean. All-spin logic-styles may offer high area-density due to small form-factor of nano-magnetic devices. However, circuit and system-level design techniques need to be explored that leaverage the specific spin-device characterisitcs to achieve energy-efficiency, performance and reliability comparable to those of CMOS. The non-volatility of nano-magnets can be exploited in the design of energy and area-efficient programmable logic. In such logic-styles, spin-devices may play the dual-role of computing as well as memory-elements that provide field-programmability. Spin-based threshold logic design is presented as an example. Emerging spintronic phenomena may lead to ultra-low-voltage, current-mode, spin-torque switches that can offer attractive computing capabilities, beyond digital switches. Such devices may be suitable for non-Boolean data-processing applications which involve analog processing. Integration of such spin-torque devices with charge-based devices like CMOS and resistive memory can lead to highly energy-efficient information processing hardware for applicatons like pattern-matching, neuromorphic-computing, image-processing and data-conversion. Finally, we discuss the possibility of using coupled spin-torque nano oscillators for low-power non-Boolean computing.

关键词： spin logic low power threshold logic analog neural networks non-Boolean programmable logic array coupled spin torque nano oscillators

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Investigation into efficient conversion methods between residue and binary systems

Investigation into efficient conversion methods between resi...

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作者： Gilbert, David E. Naval Postgraduate School

学位级别：硕士

Residue number systems (RNS) can efficiently perform addition, subtraction, and multiplication in a parallel and fault tolerant manner. Because of this, they hold significant promise for use in digital signal processing, where high speed arithmetic operators are needed. However, the difficulties in using RNS, such as magnitude comparison between two RNS values, division, and determining overflow or under- flow out of system range, have prevented more widespread use of these systems. This thesis investigates traditional methods to perform comparisons and to propose some new ones. Proposals include residue number system with quotient (RNS-Q), residue number system quotient-on-demand (RNS-QD), and pipelined conversions from tra- ditional RNS to a mixed radix representation. These proposals will be compared with traditional methods with respect to silicon area needed for implementation, speed with which they can be developed, and VLSI techniques utilized to carry out the design.

关键词： residue number systems VLSI ROM programmable logic array

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Využití jazyka C při implementaci algoritmů pro FPGA

Využití jazyka C při implementaci algoritmů pro FPGA

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作者： Jíša, Pavel Brno University of Technology

Diplomová práce se zabývá implementací algoritmů pro filtraci signálů na hradlových polích za pomoci jazyka C. Jsou v ní popsány algoritmy vytvořené pomocí j... 详细信息

Diplomová práce se zabývá implementací algoritmů pro filtraci signálů na hradlových polích za pomoci jazyka C. Jsou v ní popsány algoritmy vytvořené pomocí jazyka ImpulseC. Zaměřuje se na vytvoření jednorozměrných filtrů typu FIR a typu IIR. Práce obsahuje také implementaci dvourozměrných filtrů typu obecná konvoluční maska a Sobelův operátor. V práci je provedeno zhodnocení všech algoritmů filtrace na hradlovém poli.

关键词： programovatelná logická pole C to HDL FIR IIR Konvoluce Sobelův operátor ImpulseC programmable logic array C to HDL FIR IIR Konvoluce Sobel operator ImpulseC Text

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A FAULT MODEL FOR MULTIPLE-VALUED PLAS AND ITS EQUIVALENCES

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1994年第9期E77A卷 1527-1534页

作者： NAGATA, Y MUKAIDONO, M Univ of Ryukyus Okinawa Japan

In this paper, a fault model for multiple-valued programmable logic arrays (MV-PLAs) is proposed and the equivalences of faults of MV-PLA's are discussed. In a supposed multiple-valued NOR/TSUM PLA model, it is shown that multiple-valued stuck-at faults, multiple-valued bridging faults, multiple-valued threshold shift faults and other some faults in a literal generator circuit are equivalent or subequivalent to a multiple crosspoint fault in the NOR plane or a multiple fault of weights in the TSUM plane. These results lead the fact that multiple-valued test vector set which indicates all multiple cross-point fault and all multiple fault of weights also detects above equivalent or subequivalent faults in a MV-PLA.

关键词： EQUIVALENCES OF FAULTS FAULT MODEL MULTIPLE-VALUED logic programmable logic array TEST COMPACTION

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Controllable Current and Voltage Power sources using FPGA

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IFAC Proceedings Volumes 2012年第7期45卷 283-288页

作者： Václav Koucký Jiří Lahoda Zuzana Petránková University of West Bohemia in Pilsen Department of Applied Electronics and Telecommunications Univerzitni 26 306 14 Plzen Czech Republic

This paper deals with the development and design of digitally controllable, three-phase current and voltage power sources. The main, digitally controlled parameters of the power source are frequency, phase-shift and amplitudes of two separate sine-wave systems. Possibilities and means of implementation are discussed and a verified solution is described. The reason why this development was done is the lack of power sources on the market. The three-phase voltage and the tree-phase current systems are isolated by power transformers. Among many possibilities of voltage and current control, the method based on direct digital synthesis was selected. Control circuits of the power sources are described in VHDL and implemented in an FPGA device.

关键词： VHDL programmable logic array FPGA voltage source current source direct digital synthesis DDS

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The Use of LSI Circuits in Signalling Safety Systems

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IFAC Proceedings Volumes 1983年第4期16卷 337-342页

作者： V. Rabara R. Hronec University of Transport Zilina Czechoslovakia Research Institute of Computers Zilina Czechoslovakia

The work contains the design of the fail-safe system with the redundancy. The elimination of influence of the common mode failures is achieved by the application of two mutually complementary units which are either th... 详细信息

关键词： Dual control coding sequential machines logical microprocesor rail traffic large-scale system programmable logic array self checking checkers

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THE COMPILATION OF REGULAR EXPRESSIONS INTO INTEGRATED-CIRCUITS

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JOURNAL OF THE ACM 1982年第3期29卷 603-622页

作者： FLOYD, RW ULLMAN, JD Computer Science Department Stanford University Stanford CA Computer Science Department Stanford University Stanford CA

The design of integrated cLrcuJts to Implement arbitrary regular expressions is considered In general, a regular expression with n operands may be converted into a nondetermmlstlc fimte automaton with at most n states and n trans~uons Instead of converting the nondetermtntsttc device to a determm~suc one, two ways of implementing the nondetermlnistlc dewce directly are proposed. One approach is to produce a PLA (programmable logic array) of approximate dimensions n rows and 2n columns by representing the states of the nondetermm~stlc fimte automaton directly by columns This approach, whde theoreucally suboptimal, makes use of carefully developed technology and, because of the care with which PLA implementation has been done, may be the preferred techmque m many real sttuatlons Another approach ~s to use the hierarchical structure of the automaton produced from the regular expression by the McNaughton-Yamada algorithm to grade a hierarchical layout of the ctrcmt. This method produces a clrcmt O(x/n) on a side and ~s, to w~thin a constant factor, the best that can be done m general. © 1982, ACM. All rights reserved.

关键词： clrcmt area nondetermimsuc f'mlte automaton programmable logic array Regular expression

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