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SYMMETRIC MINIMAL COVERING PROBLEM AND MINIMAL PLAS WITH SYMMETRIC VARIABLES

IEEE TRANSACTIONS ON COMPUTERS 1985年第6期34卷 523-541页

作者： YOUNG, MH MUROGA, S UNIV ILLINOIS DEPT COMP SCIURBANAIL 61801

This paper first discusses the symmetric property of the minimal covering problem in terms of group theory and then the use of this property in the branch-and-bound method for solving the problem. Computational results on solving sample problems are shown to demonstrate the improvement of computational efficiency of the branch-and-bound method by the utilization of the symmetric property. The sample problems contain the minimal sum derivation of symmetric switching functions, as an application to the design of minimal programmable logic arrays (PLA"s). It is shown that when the minimal covering problem derived for the given switching function has symmetric permutations, the given switching function may not be symmetric; although when the given switching function is symmetric, the minimum covering problem obtained from the function is symmetric. The branch-and-bound method based on the symmetric property can be applied not only to symmetric switching functions but also to switching functions which are not symmetric, if the corresponding minimal covering problems have symmetric permutations. The method can be also applied to minimal covering problems which arise outside the minimal sum derivation problems for switching functions.

关键词： Branch-and-bound method minimal covering problem minimal sum permutation group programmable logic array symmetric function symmetric permutation

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AN ALGORITHM TO DERIVE THE COMPLEMENT OF A BINARY FUNCTION WITH MULTIPLE-VALUED INPUTS

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IEEE TRANSACTIONS ON COMPUTERS 1985年第2期34卷 131-140页

作者： SASAO, T Department of Electronic Engineering Osaka University Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

A recursive algorithm to obtain a complement of a sum-of-products expression for a binary function with p-valued inputs is presented. It produces at most pn/2 products for n-variable functions, whereas a conventional elementary algorithm produces O(tn·n(1-t)/2) products where t = 2P -1. It is 10-20 times faster than the elementary one when p = 2 and n = 8. For large practical-problems, it produces many fewer products than the disjoint sharp algorithm used by MINI. Appplications of the algorithm to PLA minimization are also presented.

关键词： Complement of logical expression logic design minimization of logical expressions multiple valued logic prime implicants programmable logic array switching theory

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A TESTABLE PLA DESIGN WITH LOW OVERHEAD AND HIGH FAULT COVERAGE

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IEEE TRANSACTIONS ON COMPUTERS 1984年第8期33卷 743-745页

作者： KHAKBAZ, J STANFORD UNIV CTR RELIABLE COMPCOMP SYST LABDEPT ELECT ENGNSTANFORDCA 94305 STANFORD UNIV CTR RELIABLE COMPCOMP SYST LABDEPT COMP SCISTANFORDCA 94305

A new design of testable PLA"s is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA"s. This design, however, is not appropriate for built-in test.

关键词： PLA folding programmable logic array testing

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INPUT VARIABLE ASSIGNMENT AND OUTPUT PHASE OPTIMIZATION OF PLAS

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IEEE TRANSACTIONS ON COMPUTERS 1984年第10期33卷 879-894页

作者： SASAO, T IBM CORP THOMAS J WATSON RES CTRYORKTOWN HTSNY 10598

A PLA minimization system having the following features is presented: 1) minimization of both two-level PLA"s and PLA"s with two-bit decoders; 2) optimal input variable assignment to the decoders; 3) optimal output phase assignment; and 4) essential prime implicants detection without generating all the prime implicants.

关键词： Adder complexity of logic circuits decoder assignment essential prime implicants logic design output phase optimization programmable logic array switching theory

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DESIGN AND APPLICATION OF SELF-TESTING COMPARATORS IMPLEMENTED WITH MOS PLAS

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IEEE TRANSACTIONS ON COMPUTERS 1984年第6期33卷 493-506页

作者： TAMIR, Y SEQUIN, CH Computer Science Division Department of Electrical Engineering and Computer Sciences University of California

A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attractive. A critical circuit in this context is a self-testing comparator. Faults in the comparator must be detected so that they do not mask discrepancies between the duplicated modules.

关键词： Concurrent error detection MOS PLA fault model duplication and matching faults in VLSI circuits programmable logic array self-testing comparator two-rail code checker

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A function-independent self-test for large programmable logic arrays

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Integration, the VLSI Journal 1983年第1期1卷 71-80页

作者： Grassl, G. Pfleiderer, H.-J. Siemens AG Research Laboratories D-8000 München 83 Germany

It has been shown that small PLAs can be made self-testing. The proposed methods however fail to handle large functions fast or result in a large overhead. Here a method is shown that can be implemented efficiently at large PLAs. The test only needs a system clock and an initialization signal, producing a go/no-go signal after an AND plane size-dependent delay. © 1983.

关键词： programmable logic array Self-test signature analysis

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The Use of LSI Circuits in Signalling Safety Systems

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IFAC Proceedings Volumes 1983年第4期16卷 337-342页

作者： V. Rabara R. Hronec University of Transport Zilina Czechoslovakia Research Institute of Computers Zilina Czechoslovakia

The work contains the design of the fail-safe system with the redundancy. The elimination of influence of the common mode failures is achieved by the application of two mutually complementary units which are either th... 详细信息

关键词： Dual control coding sequential machines logical microprocesor rail traffic large-scale system programmable logic array self checking checkers

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CONCURRENT ERROR-DETECTION AND TESTING FOR LARGE PLAS

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IEEE TRANSACTIONS ON ELECTRON DEVICES 1982年第4期29卷 756-764页

作者： KHAKBAZ, J MCCLUSKEY, EJ STANFORD UNIV DEPT COMP SCICTR RELIABLE COMPCOMP SYST LABSTANFORDCA 94305

A system of checkers is designed for concurrent error detection in large PLA's. This system combines concurrent error detection with off-line functional, testing of the PLA by using the same checker hardware for both purposes. The result is a significant saving in hardware cost. For a case example, the total hardware cost is estimated at about 37 percent of the original PLA area. The system is almost totally self-checking and, although the test patterns are not function-independent, their generation algorithm is simple. The total test time for the entire system is within the range of that of some recent PLA design schemes which were specifically aimed at simplifying off-line testing, but which have no provisions for concurrent error detection.

关键词： 1-out-of-n code checker concurrent error detection nonconcurrent PLA PLA programmable logic array testing two-rail code checker

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THE COMPILATION OF REGULAR EXPRESSIONS INTO INTEGRATED-CIRCUITS

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JOURNAL OF THE ACM 1982年第3期29卷 603-622页

作者： FLOYD, RW ULLMAN, JD Computer Science Department Stanford University Stanford CA Computer Science Department Stanford University Stanford CA

The design of integrated cLrcuJts to Implement arbitrary regular expressions is considered In general, a regular expression with n operands may be converted into a nondetermmlstlc fimte automaton with at most n states and n trans~uons Instead of converting the nondetermtntsttc device to a determm~suc one, two ways of implementing the nondetermlnistlc dewce directly are proposed. One approach is to produce a PLA (programmable logic array) of approximate dimensions n rows and 2n columns by representing the states of the nondetermm~stlc fimte automaton directly by columns This approach, whde theoreucally suboptimal, makes use of carefully developed technology and, because of the care with which PLA implementation has been done, may be the preferred techmque m many real sttuatlons Another approach ~s to use the hierarchical structure of the automaton produced from the regular expression by the McNaughton-Yamada algorithm to grade a hierarchical layout of the ctrcmt. This method produces a clrcmt O(x/n) on a side and ~s, to w~thin a constant factor, the best that can be done m general. © 1982, ACM. All rights reserved.

关键词： clrcmt area nondetermimsuc f'mlte automaton programmable logic array Regular expression

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MULTIPLE-VALUED DECOMPOSITION OF GENERALIZED BOOLEAN FUNCTIONS AND THE COMPLEXITY OF programmable logic-arrayS

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IEEE TRANSACTIONS ON COMPUTERS 1981年第9期30卷 635-643页

作者： SASAO, T Department of Electrical Engineering Osaka University Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

Generalized Boolean functions are shown to be useful for the design of programmable logic arrays (PLA"s), and the complexity of three types of PLA"s is obtained by the theory of multiple- valued decomposition. A two-level PLA consists of an AND array and an OR array, and they are cascaded to perform a two-level AND-OR circuit. A PLA with decoders consists of decoders, an AND array, and an OR array. A three-level PLA consists of a D array, an AND array, and an OR array, and they are cascaded to perform a three-level OR- AND-OR circuit. It is shown that a generalized Boolean function f(X1, X2,··, Xr):X Bni → B, where B = {0,1}, is represented by a generalized Boolean expression of 2ni-valued variables Xi; and f can be directly realized by a PLA with decoders or a three-level PLA. To realize a function of n-variables (n = 2r), the following sizes are shown to be sufficient: for a two-level PLA, (n + ½) 2n; for a PLA with two-bit decoders, 4(n + 4) 2n; for a three-level PLA, 2n+ (3n + l)√2n+ 2n2Especially in the case of PLA with two-bit decoders, the following sizes are shown to be necessary and sufficient: for an arbitrary symmetric function, 3/2(n + ½) √3n; and for a parity function, (n + ½)√ 2n.

关键词： Complexity of logic circuits functional decomposition multiple-valued logic programmable logic array symmetric function

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