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IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics

作者： Aron, Poanta Dan, Dojcsar Universitatea din Petroşani Romania

ISBN: (纸本)142440360X

In this paper is described a device used in the priming of the electrical blasting cartridge who supply the whole electrical priming energy. This device offers a much better security compare to the present similar devices because it eliminates the human factor errors. Also this device verifies and monitors the blasting line states and has the ability of blocking the blasting in improper functioning conditions. The system has the possibility of blasting line diagnosis with the stale displaying. The device was conceived and tested and satisfies the expectations in varied working conditions like underground with explosive gases or in quarries.

关键词： blasting cartridge programmable logic device explosive areas logical diagram

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Laser beam image classification methods with the use of parallel-hierarchical networks running on a programmable logic device

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OPTICAL ENGINEERING 2014年第10期53卷 1-8页

作者： Timchenko, Leonid I. Petrovskiy, Nikolay S. Kokriatskaia, Natalia I. State Econ & Technol Univ Transport Dept Telecommun Technol & Automat UA-03049 Kiev Ukraine

We examine the methods of laser beam classification and their uses. We discuss the necessity of noise filters using adaptive methods in beam reflection, such as parallel-hierarchical networks. A demonstration of this ... 详细信息

关键词： laser spot parallel-hierarchical networks programmable logic device image classification

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Complex programmable logic device-based closed-loop implementation of switched-capacitor step-down DC-DC converter for multiple output choices

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IET ELECTRIC POWER APPLICATIONS 2007年第6期1卷 926-936页

作者： Chang, Y. -H. Chaoyang Univ Technol Dept Comp Sci & Informat Engn Wufong 41349 Taichung County Taiwan

A complex programmable logic device (CPLD)-based closed-loop switched-capacitor (SC) step-down DC-DC converter is implemented for multiple output choices (9/5 V, 3.3, 2 V). For a variety of output choices, various Verilog-code control rules are designed and embedded into the CPLD-based controller for the closed-loop regulation of SC converter. Such a code-based approach makes controller design more flexible, simple and reliable. In fact, SC circuit needs no inductive element, so integrated circuit (IC) fabrication is promising for low-power VLSI applications. Here, an interleaved current-mode control is employed from battery interleaved charging to cell capacitors by two controlled current sources, so the continuous input current comes into being for lower EMI. Such a current-mode control possesses not only output robustness against source variation but also regulation capability of loading variation. Besides, the relevant theoretical analysis and control design are discussed, including conversion efficiency, lower bound of source, conversion ratio, ripple percentage, capacitance selection, closed-loop control and stability. Finally, the hardware experimental results are illustrated to show the efficacy of the CPLD-based converter.

关键词： programmable logic devices interleaved current-mode control DC-DC power convertors current-mode circuits programmable logic device switched capacitor networks closed-loop implementation switched-capacitor step-down DC-DC converter

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Design of SOA-MZI based all-optical programmable logic device (PLD)

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OPTICS COMMUNICATIONS 2010年第12期283卷 2506-2517页

作者： Chattopadhyay, Tanay Roy, Jitendra Nath WBPDCL Kolaghat Thermal Power Stn Purbamedinipur 721137 W Bengal India KTPP Township Coll Engn & Management Dept Phys Midnapur E 721171 W Bengal India

Photon being the ultimate unit of information with unmatched speed and with data package in a signal of zero mass, the techniques of computing with light may provide a way out of the limitations of computational speed and complexity inherent in electronics computing. Information processing with photon as information carrying signal has shown a high level potentiality through the researches in last few decades. The driving force behind this evolution has been the utilization of interferometric configurations that employ a semiconductor optical amplifier (SOA) as the nonlinear element in combination with cross-phase modulation to achieve switching by means of light. Here, in this paper we present an all-optical circuit of programmable logic device (PLD) with the help of SOA-MZI (Mach-Zehnder interferometer) based optical tree-structured splitter. Numerical simulation result confirming described method is reported here. This paper also explains the applicability of this scheme to perform logical and arithmetic operations in all-optical domain. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Optical switch programmable logic device Binary logic Mach-Zehnder interferometer

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Design of programmable logic device based on electro-optic effect of lithium-niobate-based Mach-Zehnder interferometers

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PHOTONIC NETWORK COMMUNICATIONS 2017年第3期33卷 356-370页

作者： Chanderkanta Singh, Neha Kumar, Santosh DIT Univ Dept Elect & Commun Engn Photon Lab Dehra Dun 248009 Uttar Pradesh India VIT Univ Dept Comp Sci & Engn Vellore 632014 Tamil Nadu India

programmable logic device (PLD) gives flexibility to implement different combinational circuits in a single device as per the requirement. In this paper, design of an optical PLD is proposed using electro-optic effect of lithium-niobate-based Mach-Zehnder interferometers (MZIs). Lithium-niobate-based MZI have spectacular ability to couple an optical input signal to a desired output port. The paper constitutes several examples of combinational logic circuits implemented with proposed device, its mathematical description and thereafter simulation using MATLAB. The study is verified using beam propagation method.

关键词： programmable logic device Electro-optic effect Mach-Zehnder interferometer Beam propagation method Optical computing

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Asynchronous Linear Combinational Circuits as a Base for programmable logic device. Binary and Ternary Cases

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IFAC-PapersOnLine 2016年第25期49卷 378-383页

作者： Latypov, Rustam Kh. Stolov, Evgeni L. Kazan Federal University Kazan420008 Russia

programmable logic devices on base of asynchronous combinational circuits with feedback are considered. The main aim of the research is to obtain a method for designing a circuit with a set of prescribed stable states or a circuit without stable states — a generator of true random numbers. Both the cases of binary and ternary logics are studied. © 2016

关键词： Computer circuits Feedback Linear networks logic devices programmable logic controllers Random number generation Timing circuits Binary logic Linear circuits programmable logic device Stable state Ternary logic True randoms

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Asynchronous Linear Combinational Circuits as a Base for programmable logic device. Binary and Ternary Cases

Asynchronous Linear Combinational Circuits as a Base for Pro...

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14th IFAC Conference on programmable devices and Embedded Systems (PDES)

作者： Latypov, Rustam Kh. Stolov, Evgeni L. Kazan Fed Univ Kazan 420008 Russia

programmable logic devices on base of asynclrronous combinational circuits with feedback are considered. The main aim of the research is to obtain a method for designing a circuit with a set of prescribed stable states or a circuit without stable states a generator of true random numbers. Both the cases of binary and ternary logics are studied. (C) 2016, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： programmable logic device asynchronous linear circuit feedback ternary logic binary logic

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High-density single-poly electrically erasable programmable logic device for embedded nonvolatile memory applications

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JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 2005年第1A期44卷 44-49页

作者： Lee, KH King, YC Natl Tsing Hua Univ Dept Elect Engn Microelect Lab STAR Grp Hsinchu 300 Taiwan

A novel electrically erasable programmable logic device (EEPLD) memory cell with new program and erase operations fabricated by a standard complementary metal-oxide-semiconductor (CMOS) logic process is presented. The cell which consists of two metal-oxide-semiconductor field effect transistor (MOSFET) transistors in series is programmed by select-gate-controlled drain avalanche hot hole injection and erased by channel hot electron injection. The cell exhibits good programming and erasing characteristics along with endurance up to 10(5) cycles, and 1000 h of data retention at 150degreesC. A new self-converged programming scheme is investigated for multilevel or analog storage. Without a P-well or an N-well serving as a coupling gate, the novel cell provides the smallest area size per bit reported for a single-poly nonvolatile memory. With its small cell size and full compatibility with the standard CMOS logic process, the novel EEPLD can be easily adopted in highly integrated VLSI systems.

关键词： EEPLD programmable logic device nonvolatile memory

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A memory-based programmable logic device using look-up table cascade with synchronous static random access memories

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JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 2006年第4B期45卷 3295-3300页

作者： Nakamura, Kazuyuki Sasao, Tsutomu Matsuura, Munehiro Tanaka, Katsumasa Yoshizumi, Kenichi Nakahara, Hiroki Iguchi, Yukihiro Kyushu Inst Technol Iizuka Fukuoka 8208502 Japan Meiji Univ Kawasaki Kanagawa 2148571 Japan

A large-scale memory-technology-based programmable logic device (PLD) using a look-LIP table (LUT) cascade is developed in the 0.35-mu m standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

关键词： look-up table cascade programmable logic device SRAM

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Design and realization of azimuth preprocess in real-time imaging processor of synthetic aperture radar with programmable logic device

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Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology 2002年第11期24卷 1659-1663页

作者： Zhang, Ju Wang, Yanfei Tan, Xiangying Inst. of Electron. Chinese Acad. of Sci. Beijing 100080 China

This paper describes the design and realization of the azimuth pre-process in the real-time imaging processor of SAR with programmable logic device by the method of sub-aperture using band-pass filter. The azimuth preprocess circuit implementation and its result are presented. It can be gotten that the circuit performance is satisfactory in operation efficiency, integration degree, implementation convenience and expandability.

关键词： Azimuth preprocess Data-collection rate reducing Imaging process programmable logic device Sub-aperture Synthetic aperture radar

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