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14th International Workshop on Computational Electronics (IWCE)

作者： Zaka, Alban Palestri, Pierpaolo Rideau, Denis Iellina, Matteo Dornel, Erwan Rafhay, Quentin Tavernier, Clement Jaouen, Herve ST Microelect 850 Rue Jean Monnet Crolles France Univ Udine DIEGM I-33100 Udine Italy MINATEC IMEP LAHC Grenoble France STG France IBM Crolles France

ISBN: (纸本)9781424493845

The embedded NOR-type Non Volatile Memory (eNVM) cell is characterized by many figures of merit. Of particular interest are the programming efficiency (PE), defined as the electron gate-to-drain current ratio (Ig/Id) during programming, and the drain disturb current (DDC), defined as the hole gate current Igh during drain disturb (Fig. 1). eNVM gate-length scaling has brought shallower and steeper Source/Drain (S/D) junctions enabling not only higher PE but also increased DDC, the latter yielding to potential reliability issues. Therefore, in the spirit of a compromise in channel/LDD implant conditions is here presented, showing a trade-off between electron and hole injection during programming and drain disturb phases, respectively.

关键词： channel-LDD implant conditions drain disturb trade-off electron gate-to-drain current ratio embedded NOR-type nonvolatile memory gate-length scaling programming efficiency random-access storage source-drain junctions

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A Survey on the Effects of Working Conditions on programming efficiency in an Educational Environment 20th

A Survey on the Effects of Working Conditions on Programming...

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20th International Conference on Computational Science and Its Applications (ICCSA)

作者： Charikova, Mariia Thapaliya, Ananga Gimaeva, Susanna Grichshenko, Alexandr Varouqa, Selina de Araujo, Luiz Jonata Pires Succi, Giancarlo Innopolis Univ Innopolis 420500 Russia

ISBN: (纸本)9783030588175;9783030588168

A recurrent concern of instructors and managers in learning and industrial sectors is how to organise the working environment to increase the productivity in tasks such as programming and software testing. Evidence of the increasing interest from different domains in this topic is the growing amount of research that has been published on physical factors (e.g., product, personnel, project and process), programming tasks (e.g., tests, questionnaires, programming, testing and debugging), and assessment methods (e.g., time, software metrics and academic grading). The objective of this paper is to survey the literature and to enable one to gain valuable insights into the relevance of physical factors to improve programming efficiency, especially in a learning environment. This study also makes recommendations on the techniques that can provide further experience for learners before joining the industrial sector. Finally, this survey suggests research directions, including an analysis of the correlation between physical factors and measurable productivity.

关键词： programming efficiency Academic environment Physical conditions Productivity factors Evaluation of productivity

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Theoretical and experimental investigation of Si nanocrystal memory device with HfO₂ high-k tunneling dielectric

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2003年第10期50卷 2067-2072页

作者： Lee, JJ Wang, XG Bai, WP Lu, N Kwong, DL Univ Texas Ctr Microelect Res Dept Elect & Comp Engn Austin TX 78758 USA

In this paper, silicon (Si) nanocrystal memory using chemical vapor deposition (CVD) HfO2 high-k dielectrics to replace the traditional SiO2 tunneling/control dielectrics has been fabricated and characterized for the first time. The advantages of this approach for improved nanocrystal memory operation have also been studied theoretically. Results show that due to its unique band asymmetry in programming and retention mode, the use of high-k dielectric on Si offers lower electron barrier height at dielectric/Si interface and larger physical thickness, resulting in a much higher J(g,programming)/J(g,retention) ratio than that in SiO2 and therefore faster programming and longer retention. The fabricated device with CVD HfO2 shows excellent programming efficiency and data-retention characteristics, thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO2 as compared with SiO2 of the same electrical oxide thickness (EOT). It also shows clear single-electron charging effect at room temperature and superior data endurance up to 10(6) write/erase cycles.

关键词： data endurance data retention HfO2 high-k di-electric nanocrystal memory programming efficiency

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CHISEL flash EEPROM - Part I: Performance and scaling

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2002年第7期49卷 1296-1301页

作者： Mahapatra, S Shukuri, S Bude, J Bell Labs Lucent Technol Agere Syst Murray Hill NJ 07974 USA Hitachi Ltd Semicond & Integrated Circuits Grp Tokyo 198 Japan

In this work, we demonstrate the feasibility of using channel initiated secondary electron (CHISEL) programming in high-density flash memories containing fully scaled memory cells. We discuss programming performance, cell channel length scaling, endurance, and reliability of single cells and large arrays. In Part I of this work, we show successful CHISEL programming operation in fully scaled flash cells having channel lengths down to 0.22 mum. Compared to conventional channel hot electron (CHE) programming, CHISEL operation shows faster programming for identical drain bias, and lower power consumption for similar programming speed. The effect of channel length scaling on CHISEL operation and related device optimization is discussed using measurements and device simulation. Measurement on optimized floating gate contacted devices having channel length down to 0.14 mum show good programming efficiency under CHISEL operation. The reliability and endurance of CHISEL operation in single cells and large arrays are discussed in Part 11 of this work.

关键词： channel hot electron (CHE) channel initiated secondary electron (CHISEL) device scaling flash EEPROM MOSFET programming efficiency

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Investigation of Physically Unclonable Functions Using Flash Memory for Integrated Circuit Authentication

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2015年第2期14卷 384-389页

作者： Kim, Moon-Seok Moon, Dong-Il Yoo, Sang-Kyung Lee, Sang-Han Choi, Yang-Kyu ETRI Attached Inst Taejon 305600 South Korea Korea Adv Inst Sci & Technol Dept Elect Engn Taejon 305701 South Korea

Flash memory devices are investigated to confirm their application as physically unclonable functions (PUFs). Inherent fluctuations in the characteristics of flash memory devices, even with identical fabrication processes, produce different outputs, which are useful for device fingerprints. A difference in programming/erasing efficiency arises from a widely distributed threshold voltage. However, statistical fluctuations in the threshold voltage represent an advantage for PUF applications. The characteristics of PUFs, such as their unclonability, uncontrollability, unpredictability, and robustness, are investigated using fabricated flash memory devices. A simulation study is performed to support the experimental results and to show that the unpredictability is induced by variations in the gate dielectric thickness.

关键词： Flash memory SONOS (silicon/oxide/nitride/oxide/silicon) gate-all-around (GAA) transistors process variation physically unclonable function (PUF) programming efficiency device fingerprint device authentication

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Machine Learning Computers With Fractal von Neumann Architecture

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IEEE TRANSACTIONS ON COMPUTERS 2020年第7期69卷 998-1014页

作者： Zhao, Yongwei Fan, Zhe Du, Zidong Zhi, Tian Li, Ling Guo, Qi Liu, Shaoli Xu, Zhiwei Chen, Tianshi Chen, Yunji Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100190 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China Cambricon Technol Beijing Peoples R China Chinese Acad Sci Inst Software Beijing 100190 Peoples R China CAS Ctr Excellence Brain Sci & Intelligence Techn Shanghai Res Ctr Brian Sci & Brain Inspired Intel Inst Brain Intelligence Technol Zhangjiang Lab BITZfLab Beijing Peoples R China

Machine learning techniques are pervasive tools for emerging commercial applications and many dedicated machine learning computers on different scales have been deployed in embedded devices, servers, and data centers. Currently, most machine learning computer architectures still focus on optimizing performance and energy efficiency instead of programming productivity. However, with the fast development in silicon technology, programming productivity, including programming itself and software stack development, becomes the vital reason instead of performance and power efficiency that hinders the application of machine learning computers. In this article, we propose Cambricon-F, which is a series of homogeneous, sequential, multi-layer, layer-similar, and machine learning computers with same ISA. A Cambricon-F machine has a fractal von Neumann architecture to iteratively manage its components: it is with von Neumann architecture and its processing components (sub-nodes) are still Cambricon-F machines with von Neumann architecture and the same ISA. Since different Cambricon-F instances with different scales can share the same software stack on their common ISA, Cambricon-Fs can significantly improve the programming productivity. Moreover, we address four major challenges in Cambricon-F architecture design, which allow Cambricon-F to achieve a high efficiency. We implement two Cambricon-F instances at different scales, i.e., Cambricon-F100 and Cambricon-F1. Compared to GPU based machines (DGX-1 and 1080Ti), Cambricon-F instances achieve 2.82x, 5.14x better performance, 8.37x, 11.39x better efficiency on average, with 74.5, 93.8 percent smaller area costs, respectively. We further propose Cambricon-FR, which enhances the Cambricon-F machine learning computers to flexibly and efficiently support all the fractal operations with a reconfigurable fractal instruction set architecture. Compared to the Cambricon-F instances, Cambricon-FR machines achieve 1.96x, 2.49x better per

关键词： Machine learning Computers Fractals programming Computer architecture Graphics processing units Matrix decomposition Machine learning architecture neural networks programming efficiency

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CHISEL programming operation of scaled NOR flash EEPROMs - Effect of voltage scaling, device scaling and technological parameters

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2003年第10期50卷 2104-2111页

作者： Mohapatra, NR Nair, DR Mahapatra, S Rao, VR Shukuri, S Bude, JD Indian Inst Technol Dept Elect Engn Bombay 400076 Maharashtra India Semicond & Integrated Circuits Grp Tokyo Japan Agere Syst Allentown PA USA

The impact of programming biases, device scaling and variation of technological parameters on channel initiated secondary electron (CHISEL) programming performance of scaled NOR Flash electrically erasable programmable read-only memories (EEPROMs) is studied in detail. It is shown that CHISEL operation offers faster programming for all bias conditions and remains highly efficient at lower biases compared to conventional channel hot electron (CHE) operation. The physical mechanism responsible for this behavior is explained using full band Monte Carlo simulations. CHISEL programming efficiency is shown to degrade with device scaling, and various technological parameter optimization schemes required for its improvement are explored. The resulting increase in drain disturbs is also studied and the impact of technological parameter optimization on the programming performance versus drain disturb tradeoff is analyzed. It is shown that by judicious choice of technological parameters the advantage of CHISEL programming can be maintained for deeply scaled electrically erasable programmable read-only memory (EEPROM) cells.

关键词： channel hot electron (CHE) channel initiated secondary electron (CHISEL) device scaling Flash electrically erasable programmable read-only memories (EEPROMs) hot carriers monte carlo simulation programming efficiency

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Improved programming performance of EEPROM/flash cell using post-poly-Si gate N₂O annealing

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ELECTRONICS LETTERS 1999年第13期35卷 1112-1114页

作者： Huang, KC Fang, YK Yaung, DN Kuo, DS Wang, CS Liang, MS Natl Cheng Kung Univ Dept Elect Engn VLSI Technol Lab Tainan 70101 Taiwan Taiwan Semicond Mfg Co Ltd Hsinchu Taiwan

The effect of post poly-Si N2O annealing on the programming performance and reliability of split-gate source-side-injection EEPROM/flash memory cells has been investigated. It is found that by employing post-poly-Si gate N2O-annealing, the programming efficiency and the immunity to program disturbances can be significantly improved.

关键词： integrated memory circuits EEPROM/flash cell N2O annealing N2O annealing post-poly-Si gate annealing programming efficiency Semiconductor integrated circuits Si Annealing processes in semiconductor technology flash memories polysilicon gate Maintenance and reliability Reliability PLD programming integrated circuit reliability Memory circuits split-gate memory cells reliability programming performance improvement program disturbances immunity source-side-injection memory cells

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Cryogenic characterisation of 55 nm SONOS charge-trapping memory in AC and DC modes

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ELECTRONICS LETTERS 2020年第4期56卷 199-+页

作者： Fan, Lin-Jie Bi, Jin-Shun Xu, Yan-Nan Xi, Kai Ma, Yao Liu, Ming Majumdar, Sandip Chinese Acad Sci Key Lab Microelect Device & Integrated Technol Inst Microelect Beijing 100029 Peoples R China Sichuan Univ Coll Phys Chengdu 610065 Sichuan Peoples R China ICFAI Univ Sch Phys Agartala 799210 India Univ Chinese Acad Sci Beijing 100049 Peoples R China

The electrical responses of 55 nm silicon-oxide-nitride-oxide-silicon (SONOS) memory cells have been investigated under cryogenic conditions, and the changes of the read curves of SONOS in AC mode (programmed/erased with pulse voltage) and DC mode (programmed/erased with direct voltage sweeping) at low temperatures are compared. The experimental results show that with the decrease of temperature, the subthreshold swing of SONOS decreases, whereas the on-state current of SONOS increases. The difference in AC and DC operations causes the threshold voltage of the read curve to drift accordingly, leading to the different change in the memory window. However, in both modes of operations, the efficiencies of programming and erasing decrease at cryogenic temperatures. It is analysed that the reduction of programming efficiency at cryogenic temperatures is caused by the decrease in the quantity of pre-tunnelling electrons. The reduction in erasing efficiency is attributable to the suppression of the Poole-Frenkel effect at low temperatures, which makes it more difficult for electrons to be de-trapped.

关键词： integrated circuit reliability silicon Poole-Frenkel effect silicon compounds tunnelling random-access storage elemental semiconductors cryogenic electronics low-temperature techniques cryogenic characterisation cryogenic conditions AC mode pulse voltage direct voltage SONOS threshold voltage read curve memory window cryogenic temperatures silicon-oxide-nitride-oxide-silicon memory cells SONOS charge-trapping memory DC modes direct voltage sweeping subthreshold swing programming efficiency pre-tunnelling electron quantity Poole-Frenkel effect suppression on-state current electrical responses size 55 0 nm SiON-Si

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Device Considerations of Planar NAND Flash Memory for Extending towards Sub-20nm Regime

Device Considerations of Planar NAND Flash Memory for Extend...

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5th IEEE International Memory Workshop (IMW)

作者： Park, Youngwoo Lee, Jaeduk Samsung Elect Co Ltd Memory Technol Dev Team Semicond R&D Ctr Hwasung 445701 Gyeonggi South Korea

ISBN: (纸本)9781467361699

Device considerations of planar NAND flash memory for extending towards sub-20nm regime have been reviewed. A transient deep-depletion phenomenon of p-type floating gate, which affects the program efficiency of a scaled device, is described. The endurance of the p-type floating gate has been improved with an aid of hole compensation on the charge trapping. Meanwhile, solutions are required to overcome the lowering of the boosting potential by the BTBT generation with increased lateral electric field between the channels as well as the BTBT generation with increased vertical electric field. Furthermore, the conventional DIBL effect also significantly affects V-T shift on the scaled-NAND string. Regarding the reliability, the electric field crowding on the top of the floating gate should be relieved and it has been revealed that the endurance behavior has been changed by the increase of edge tunneling current during the erase operation.

关键词： NAND flash memory programming efficiency Scale down p-type Floating Gate Reliability Endurance model

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