Short-term instability is one of the key challenges for redox-based resistive random-access memory (ReRAM) reaching practical applications in the field of neuromorphic computing. Developing programming schemes that ba...
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Short-term instability is one of the key challenges for redox-based resistive random-access memory (ReRAM) reaching practical applications in the field of neuromorphic computing. Developing programming schemes that balance resistance fine-tuning with short-term stability is crucial for improving the reliability of ReRAM devices. In this work, we explore the impact of programming schemes on the short-term variability of valence change mechanism (VCM)-based filamentary ReRAM devices. We design three programming schemes: a baseline multi-pulse scheme, a single short-pulse scheme, and a single long-pulse scheme. By comparing the programming statistics of the one-transistor-one-resistor (1T1R) structures under different schemes and analyzing their evolution over time, we propose the hypothesis that the number and width of pulses influence the filament size and internal distribution of oxygen vacancies, and thus the short-term stability of ReRAM devices. We employ three-dimensional Kinetic Monte Carlo simulation, constructing filaments of varying sizes and adjusting the oxygen vacancy distribution to simulate the outcomes of different programming schemes. The simulation results align with experimental findings. Based on existing experimental data and modeling studies, we propose programming strategies that balance programmability and reliability for VCM-based filamentary ReRAM devices.
Exploiting multi-level cell (MLC) in distributed memristor-based applications not only increases the memory density by providing multi-bit memory elements, but also enables efficient implementation of signed-digit (SD...
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ISBN:
(纸本)9781450364751
Exploiting multi-level cell (MLC) in distributed memristor-based applications not only increases the memory density by providing multi-bit memory elements, but also enables efficient implementation of signed-digit (SD) arithmetic circuits with multi-value registers. As a binary memory unit for distributed deployment, memristive voltage divider (MVD) exhibits promising features and characteristics, e.g. reduced energy consumption, enhanced endurance and read-while-write capability. In this work we investigate programming schemes for writing multiple levels into MVD. We explore traditional memristor programming methods namely write pulse amplitude, write pulse duration and current limited write pulse as well as feedback-based write mechanism enabled by the MVD's read-while-write feature. Based on this analysis we then a) classify the presented schemes with respect to the number of achievable levels and energy consumption. b) give design insights into composing circuits with multi-level MVD.
High-density and reliable multilevel-cell (MLC) resistive random access memory (RRAM) is expected to meet the ever-increasing demand for on-chip weight storages in the intelligent edge devices. However, due to the dev...
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High-density and reliable multilevel-cell (MLC) resistive random access memory (RRAM) is expected to meet the ever-increasing demand for on-chip weight storages in the intelligent edge devices. However, due to the device variations, many write-and-verify (WAV) iterations are usually required to program the RRAM cell, which causes high power consumption, long latency, and degradation on the memory lifetime. To address this issue, we propose a write-verify-free MLC RRAM macro for weight storage with 1) a cascode-current-mirror multibit write (CCM-MW) driver and 2) a nonbinary programming scheme (NB-PS) with a radix not greater than 2. A 180-nm 400-Kb RRAM test chip is demonstrated in silicon. For 2-bit-per-cell MLC storage, the value error rates can be reduced by 24.13% after introducing two redundant bits (RBDs). In addition, compared to the single-level cell (SLC) storage scheme, a 37.50% reduction in the number of cells can be achieved to store the ResNet-8 model with a 0.79% loss in inference accuracy without the need for WAV iterations.
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