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real-time image processing for crop/weed discrimination in maize fields

COMPUTERS AND ELECTRONICS IN AGRICULTURE 2011年第2期75卷 337-346页

作者： Burgos-Artizzu, Xavier P. Ribeiro, Angela Guijarro, Maria Pajares, Gonzalo Spanish Natl Res Council Ctr Automat & Robot UPM CSIC GPA Madrid Spain Univ Complutense Madrid Dept Ingn Software & Inteligencia Artificial E-28040 Madrid Spain

This paper presents a computer vision system that successfully discriminates between weed patches and crop rows under uncontrolled lighting in real-time. The system consists of two independent subsystems, a fast image processing delivering results in real-time (Fast image processing, FIP). and a slower and more accurate processing (Robust Crop Row Detection, RCRD) that is used to correct the first subsystem's mistakes. This combination produces a system that achieves very good results under a wide variety of conditions. Tested on several maize videos taken of different fields and during different years, the system successfully detects an average of 95% of weeds and 80% of crops under different illumination, soil humidity and weed/crop growth conditions. Moreover, the system has been shown to produce acceptable results even under very difficult conditions, such as in the presence of dramatic sowing errors or abrupt camera movements. The computer vision system has been developed for integration into a treatment system because the ideal setup for any weed sprayer system would include a tool that could provide information on the weeds and crops present at each point in real-time, while the tractor mounting the spraying bar is moving. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Computer vision Precision Agriculture Weed detection real-time image processing

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real-time image processing with dynamically reconfigurable architecture

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real-time IMAGING 2003年第5期9卷 297-313页

作者： Kessal, L Abel, N Demigny, D Cergy Pontoise Univ CNRS ENSEA ETISUMR 8051 Cergy Pontoise France

During the last few years, many architectures using processors and/or field programmable gate arrays (FPGA) were built to accelerate computationally complex problems. The processors allow a high degree of flexibility, whilst the FPGA implementation might be considerably faster. In spite of the possibility of reconfiguring the conventional FPGA an unlimited number of time, many of these architectures were built to compute a single application. If the FPGA is reconfigured several times to execute various algorithms, the configuration time increases and degrades global performances. In this paper, an architecture dedicated to real-time image processing using the AT40K reconfigurable FPGA family is presented (ARDOISE project(1)). We discuss Dynamic Reconfiguration (or Run-time Reconfiguration), a technique based on the reuse of the same device (an FPGA configured on the fly) by scheduling the execution of different algorithms building an application. The techniques and the tools developed to test and use the system are described. (C) 2003 Elsevier Ltd. All rights reserved.

关键词： ARCHITECTURE dynamic reconfiguration Field programmable gate arrays real-time image processing Reconfigurable architectures

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real-time image processing of TOF range images using a reconfigurable processor system

Real-time image processing of TOF range images using a recon...

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Conference on Videometrics, Range Imaging, and Applications XI

作者： Hussmann, S. Knoll, F. Edeler, T. Westcoast Univ Appl Sci Inst Machine Vis Technol Ma Vi Tec D-25746 Heide Germany

ISBN: (纸本)9780819486813

During the last years, time-of-Flight sensors achieved a significant impact onto research fields in machine vision. In comparison to stereo vision system and laser range scanners they combine the advantages of active sensors providing accurate distance measurements and camera-based systems recording a 2D matrix at a high frame rate. Moreover low cost 3D imaging has the potential to open a wide field of additional applications and solutions in markets like consumer electronics, multimedia, digital photography, robotics and medical technologies. This paper focuses on the currently implemented 4-phase-shift algorithm in this type of sensors. The most time critical operation of the phase-shift algorithm is the arctangent function. In this paper a novel hardware implementation of the arctangent function using a reconfigurable processor system is presented and benchmarked against the state-of-the-art CORDIC arctangent algorithm. Experimental results show that the proposed algorithm is well suited for real-time processing of the range images of TOF cameras.

关键词： Phase measurement phase-shift algorithm photonic mixer devices (PMD) time-of-flight (TOF) optical distance measurement component real-time image processing instruction set interpretation custom instructions

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real-time image processing of TOF range images using a single shot image capture algorithm

Real-time image processing of TOF range images using a singl...

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29th Annual IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

作者： Hussmann, Stephan Hermanski, Alexander West Coast Univ Appl Sci Dept Elect Engn & Informat Technol Heide Germany West Coast Univ Appl Sci Inst Machine Vision Technol Heidelberg Germany

ISBN: (纸本)9781457717710

During the last years, time-of-Flight sensors achieved a significant impact onto research fields in machine vision. In comparison to other common 3D sensing devices they combine the advantages of active sensors providing accurate distance measurements and camera-based systems recording a 2D matrix at a high frame rate. This paper focuses on the currently implemented 4-phase-shift algorithm to calculate the range image in this type of sensors. A new approach is presented which increases the range calculation time by a factor of four. Experimental results show that the proposed algorithm is well suited for real-time processing of the range images of TOF cameras.

关键词： Phase measurement phase-shift algorithm photonic mixer devices (PMD) time-of-flight (TOF) optical distance measurement component real-time image processing

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real-time image processing in A Multi-UAV System for Structural Surveillance Through IoT Platform

Real-time Image Processing in A Multi-UAV System for Structu...

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Conference on real-time image processing and Deep Learning

作者： Falcon, Jose Mehrubeoglu, Mehrube Rangel, Pablo Texas A&M Univ Corpus Christi Elect Engn Program Dept Engn Corpus Christi TX 78412 USA

ISBN: (纸本)9781510650817;9781510650800

The use of location and instruction markers for multi-path planning enhancement in any set of unmanned aerial systems' tasks is crucial to the coordination and effectiveness of the individual unmanned aerial vehicles (UAVs). This research implements OpenCV algorithms that allow multiple UAVs to use ArUco markers to receive data related to location and instruction for the purposes of multi-path planning. OpenCV algorithms are utilized to develop vision-based solutions that will enhance the real-time capabilities of the UAVs. The final goal for the multi-drone system entails inspecting and surveying objects for structural damage and applying the developed image processing algorithms to collected images to determine the significance of damage. This project utilizes OpenCV and Python libraries for multi-drone pathway planning by collecting, transmitting, and displaying real-world industrially valuable data over the network infrastructure as an application of Internet of Things (IoT).

关键词： unmanned aerial vehicle UAV OpenCV ArUco marker Internet of Things real-time image processing

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real-time image processing platform for the correction of X-ray detector related artifacts

Real-time image processing platform for the correction of X-...

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Medical Imaging 1999 Conference

作者： Jung, N Gipp, T Jacobs, H Paul, H Philips Res Labs D-52066 Aachen Germany

ISBN: (纸本)0819431311

Novel detector systems based on large area thin film electronics have the potential for an excellent image quality. However, the raw images derived from such detectors show various artifacts that have to be removed in real-time before the image is visualized to the user. Hence, superior flexibility in the applicable algorithms, sufficient system performance scalability, and a short processing delay are the key factors for the choice of a well suited processing platform due to the nature of the artifacts and due to the requirements of the medical applications. Further the very rapid progress in the available processing hardware has to be taken into account. A system comprising multiple nodes of a modern digital signal processor family can properly fulfill the key demands: high processing performance, strong data handling, full programmability and a processor family roadmap linked to state-of-the-art chip technology. Architecture principles, implementation aspects and first results derived from our new demonstrator system based on the modern SHARC DSP family are presented. The given first generation of the multiprocessor system corrects the basic artifacts at pixel rates of 50 Mpixel/s in 32-bit floating point arithmetic at, a processing delay in the millisecond range.

关键词： dynamic x-ray imaging system all-solid-state x-ray detectors real-time image processing

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Special issue on reconfigurable architecture for real-time image processing

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JOURNAL OF real-time image processing 2008年第3期3卷 117-118页

作者： Akil, Mohamed ESIEE Unite Mixte Rech CNRS UMLVPE ESIEE UMR 8049 Inst Gaspar Monge Dept Comp Sci F-93162 Noisy Le Grand France

The performance requirements of image processing applications have led to increase in the computing power of implementation platforms, in particular when real-time constraints are to be met. image processing applications may consist of different standards, or different algorithms used at different stages of the processing chain. The computing paradigm of reconfigurable architectures promises a trade-off between flexibility and performance. Reconfigurable architectures can exploit fine-grain (more suitable for low-level and medium-level operations in the image processing chain) and coarse-grain parallelism (more suitable for high-level operations in the image processing chain). Many reconfigurable architectures have been constructed specifically for image processing using different processors and dedicated circuits such as ASICs and FPGAs.

关键词： time constraints linearly ordered set Reconfigurable architectures real-time image processing computational power image processing LOW LEVEL

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Bit-Level Pipelined 2-D Digital Filters for real-time image processing

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1991年第1期1卷 22-34页

作者： Wu, Cheng-Wen Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30043 Taiwan

Bit-level systolic arrays for real-time 2-D FIR and IIR filters am presented. Two-dimensional Iteration and retiming techniques an depicted to illustrate block pipeline 2-D IIR filters, which guarantee high throughput operation for real-time applications. The block (parallel) systolic architectures are refined down to the bit level. By doing so we increase the filter's throughput rate as well as decrease the filter's development and manufacturing costs. We Improve the AP figure from O(N(2)W(3)) by the previous design to O(N(2)W(2)), Le., by a factor of O(W). Pipelining at the bit level is the major reason for this improvement. Another advantage of our design Is that It has a simpler wire routing and control circuitry. In summary. our systolic-array realizations are 1) more cost effective;2) more regular structurally;3) composed of bit-level cells and latches;4) fully pipelined at The bit level.

关键词： Bit Level Latch Device Component two-dimensional digital filters Infinite impulse response filters real-time image processing Filters

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A low-power integrated smart sensor with on-chip real-time image processing capabilities

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EURASIP JOURNAL ON APPLIED SIGNAL processing 2005年第7期2005卷 1062-1070页

作者： Barbaro, M Raffo, L Univ Cagliari Dept Elect & Elect Engn I-09123 Cagliari Italy

A low-power, CMOS retina with real-time, pixel-level processing capabilities is presented. Features extraction and edge enhancement are implemented with fully programmable ID Gabor convolutions. An equivalent computation rate of 3 GOPs is obtained at the cost of very low-power consumption (1.5 mu W per pixel), providing real-time performances (50 microseconds for overall computation, 0.5GOPs/mW). Experimental results from the first realized prototype show a very good matching between measures and expected outputs.

关键词： smart sensors bioinspired circuits real-time image processing

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Adaptive real-time image processing exploiting two dimensional reconfigurable architecture

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JOURNAL OF real-time image processing 2009年第2期4卷 109-125页

作者： Braun, Lars Goehringer, Diana Perschke, Thomas Schatz, Volker Huebner, Michael Becker, Juergen Univ Karlsruhe ITIV D-76131 Karlsruhe Germany FGAN FOM Forschungsinst Optron & Mustererkennung D-76275 Ettlingen Germany

Fine grained reconfigurable architectures, like Xilinx field programmable gate arrays (FPGAs) provide a high flexibility through runtime re-programming, called dynamic and partial reconfiguration. This feature allows for runtime adaptation of the system architecture and behavior configured on the FPGA. The exploitation of this feature enables to load video image processing algorithms on-demand in order to adapt the configuration in correspondence to the changing requirements of the application depending on the image content. For high resolution sensor images, this novel computing paradigm can provide a huge benefit in power reduction and performance gain for actual and future embedded electronic systems. This paper presents a two dimensional system approach exploiting dynamic and partial reconfiguration in order to adapt the system architecture to the actual requirements of image processing applications. The methodology of runtime reconfiguration can be exploited beneficially for highly adaptive multiprocessor systems. Such systems, different from the traditional static approach for multi-and many-core architectures have the advantage, for providing computational performance directly linked to the requirements of the application. The architecture presented in this paper allows for adapting the processing elements as well as the communication infrastructure which is a novel 2D switch-based Network-on-Chip. The presented approach follows and extends the actual trend in computer science of using many- and multi-core processors for bridging the gap between required computation performance for future application in the field of image processing.

关键词： real-time image processing Field programmable gate array Dynamic and partial reconfiguration Network-on-Chip Reconfigurable hardware MPSoC

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