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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Kermani, Mehran Mozaffari Ramadoss, Rajkumar Azarderakhsh, Reza Rochester Inst Technol Dept Elect & Microelect Engn Rochester NY 14623 USA Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA

ISBN: (纸本)9781479953417

Various optimized coordinate rotation digital computer (CORDIC) designs have been proposed to date. Nonetheless, in the presence of natural faults, such architectures could lead to erroneous outputs. In this paper, we propose error detection schemes for CORDIC architectures used vastly in applications such as complex number multiplication, and singular value decomposition for signal and image processing. To the best of our knowledge, this work is the first in providing reliable architectures for these variants of CORDIC. We present three variants of recomputing with encoded operands to detect both transient and permanent faults. The overheads and effectiveness of the proposed designs are benchmarked through Xilinx FPGA implementations and error simulations. The proposed approaches can be tailored based on overhead tolerance and the reliability constraints to achieve.

关键词： Coordinate rotation digital computer recomputing with encoded operands reliability

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Efficient error detection architectures for CORDIC through recomputing with encoded operands

Efficient error detection architectures for CORDIC through r...

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International Symposium on Circuits and Systems

作者： Mehran Mozaffari Kermani Rajkumar Ramadoss Reza Azarderakhsh Department of Electrical and Microelectronic Engineering Rochester Institute of Technology Rochester NY 14623 Department of Computer Engineering Rochester Institute of Technology Rochester NY 14623

ISBN: (纸本)9781479953424

关键词： reliability Coordinate rotation digital computer recomputing with encoded operands

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Secure Hardware Constructions for Fault Detection of Lattice-Based Post-Quantum Cryptosystems

Secure Hardware Constructions for Fault Detection of Lattice...

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作者： Sarker, Ausmita University of South Florida

学位级别：Ph.D., Doctor of Philosophy

The advent of quantum computers and the exponential speed-up of quantum computation will render classical cryptosystems insecure, as that can solve current encryptions in minutes, resulting in a catastrophic failure of privacy preservation and data security. Through the standardizing of quantum-resistant public-key cryptography algorithms, the National Institute of Standards and Technology (NIST) is evaluating potential candidates to thwart such quantum attacks. In this dissertation, countermeasures against fault attacks are proposed to secure various lattice-based cryptosystems, one of the most promising post-quantum cryptosystems. Fault detection architectures for crucial building blocks of lattice-based cryptosystems, i.e., number-theoretic transform, ring polynomial multiplication, and ring learning with error are introduced. Moreover, the secure hardware architecture of post-quantum key encapsulation mechanism SABER and the signature scheme Falcon are explored. The proposed architectures can also detect natural faults, caused by device malfunctions, which are crucial to proper functionalities of sensitive and secure deeply-embedded systems with stringent constraints.

关键词： Cryptography Number-theoretic transform recomputing with encoded operands Ring learning with error Ring polynomial multiplication

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Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2017年第1期64卷 208-216页

作者： Kermani, Mehran Mozaffari Singh, Vineeta Azarderakhsh, Reza Rochester Inst Technol Dept Microelect & Elect Engn Rochester NY 14623 USA Florida Atlantic Univ Dept Comp & Elect Engn & Comp Sci Boca Raton FL 33431 USA Florida Atlantic Univ Boca Raton FL 33431 USA

The Viterbi algorithm is commonly applied to a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices. In this paper, efficient error detection schemes for architectures based on low-latency, low-complexity Viterbi decoders are presented. The merit of the proposed schemes is that reliability requirements, overhead tolerance, and performance degradation limits are embedded in the structures and can be adapted accordingly. We also present three variants of recomputing with encoded operands and its modifications to detect both transient and permanent faults, coupled with signature-based schemes. The instrumented decoder architecture has been subjected to extensive error detection assessments through simulations, and application-specific integrated circuit (ASIC) [32 nm library] and field-programmable gate array (FPGA) [Xilinx Virtex-6 family] implementations for benchmark. The proposed fine-grained approaches can be utilized based on reliability objectives and performance/implementation metrics degradation tolerance.

关键词： Error detection look-ahead technique recomputing with encoded operands trellis

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