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AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2016年第1期27卷 66-77页

作者： Abad, Pablo Prieto, Pablo Puente, Valentin Gregorio, Jose-Angel Univ Cantabria Comp Architecture Grp Santander 39005 Spain

This work shows how by adapting replacement policies in contemporary cache hierarchies it is possible to extend the lifespan of a write endurance-limited main memory by almost one order of magnitude. The inception of this idea is that during cache residency 1) blocks are modified in a bimodal way: either most of the content of the block is modified or most of the content of the block never changes, and 2) in most applications, the majority of blocks are only slightly modified. When those facts are considered by the cache replacement algorithms, it is possible to significantly reduce the number of bit-flips per write-back to main memory. Our proposal favors the off-chip eviction of slightly modified blocks according to an adaptive replacement algorithm that operates coordinately in L2 and L3. This way it is possible to improve significantly system memory lifetime, with negligible performance degradation. We found that using a few bits per block to track changes in cache blocks with respect to the main memory content is enough. With a slightly modified sectored LRU and a simple cache performance predictor it is possible to achieve a simple implementation with minimal cost in area and no impact on cache access time. On average, our proposal increases the memory lifetime obtained with an LRU policy up to 10 times (10 x) and 15 times (15 x) when combined with other memory centric techniques. In both cases, the performance degradation could be considered negligible.

关键词： Cache memories memory hierarchy replacement algorithm endurance

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Web cache management based on the expected cost of web objects

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INFORMATION AND SOFTWARE TECHNOLOGY 2005年第9期47卷 609-621页

作者： Bahn, H Ewha Womans Univ Dept Comp Sci & Engn Seoul 120750 South Korea

With the recent explosion in usage of the World Wide Web, Web caching has become increasingly important. However, due to the non-uniform cost/size property of data objects in this environment, design of an efficient caching algorithm becomes an even more difficult problem compared to the traditional caching problems. In this paper, we propose the Least Expected Cost (LEC) replacement algorithm for Web caches that provides a simple and robust framework for the estimation of reference probability and fair evaluation of non-uniform Web objects. LEC evaluates a Web object based on its cost per unit size multiplied by the estimated reference probability of the object. This results in a normalized assessment of the contribution to the cost-savings ratio, leading to a fair replacement algorithm. We show that this normalization method finds optimal solution under some assumptions. Trace-driven simulations with actual Web cache logs show that LEC offers the performance of caches more than twice its size compared with other algorithms we considered. Nevertheless, it is simple, having no parameters to tune. We also show how the algorithm can be effectively implemented as a Web cache replacement module. (c) 2004 Elsevier B.V. All rights reserved.

关键词： world wide web cache caching proxy replacement algorithm

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A RECONFIGURABLE ATM SWITCH FABRIC FOR FAULT TOLERANCE AND TRAFFIC BALANCING

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IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 1991年第8期9卷 1205-1217页

作者： YANG, SC SILVESTER, JA UNIV SO CALIF DIV COMP ENGNLOS ANGELESCA 90089

We propose a large-scale ATM switch fabric that can be constructed with currently feasible technology. A modular design that is carefully matched to technological design constraints makes large ATM switches (> 1000 x 1000) feasible. Based on our analysis of the technology, we find that module interconnection becomes the bottleneck for a large fast packet switch rather than the topology of the interconnection network. For a large switch, reliability becomes critical, so particular attention is paid to fault tolerance which is achieved by dynamic reconfiguration of the module interconnection network. The proposed design significantly improves system reliability with relatively low hardware overhead. An abstract model Of the replacement problem for our design is presented and the problem is transformed into a well-known assignment problem. The maximum fault tolerance is found and a fast replacement algorithm is presented. The reconfiguration capability can also be used to ameliorate imbalanced traffic flows. We formulate this traffic flow assignment problem for our switch fabric and we show that the problem is NP-hard. We then propose a simple heuristic algorithm and give an example.

关键词： dynamic reconfiguration Traffic flow Switches ATM switch Traffic Bottlenecks Fault tolerance replacement algorithm switch fabric

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DABC-NV: A Buffer Cache Architecture for Mobile Systems with Heterogeneous Flash Memories

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2012年第4期58卷 1237-1245页

作者： Park, Junseok Lee, Eunji Bahn, Hyokyung Seoul Natl Univ Sch Comp Sci & Engn Seoul 151742 South Korea Ewha Womans Univ Dept Comp Sci & Engn Seoul South Korea

Flash memory is widely used in mobile consumer electronics devices due to its good properties such as small size, shock resistance, and low-power consumption. However, the cost of flash memory is still high to accommodate ever-growing mobile applications and multimedia contents. Using MLC (multi-level cell) technologies is an efficient solution to extend the storage capacity, but it degrades the performance of flash memory significantly compared to the original storage based on SLC (single-level cell) technologies. To bridge the characteristics of the two technologies, this paper presents a new buffer cache management scheme that uses both MLC and SLC together and considers their heterogeneous characteristics. By allocating cache space based on the characteristics of each storage media as well as I/O operation types and reference history of buffered blocks, the proposed scheme improves the I/O performance of mobile systems by 24% on average and up to 180% compared to the CLOCK algorithm. Moreover, it guarantees high reliability of file data by adopting recently emerging non-volatile RAMs in a certain portion of the buffer cache.(1)

关键词： buffer cache replacement algorithm NAND flash memory MLC flash memory NVRAM

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Beyond Belady to Attain a Seemingly Unattainable Byte Miss Ratio for Content Delivery Networks

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2024年第11期35卷 1949-1963页

作者： Wang, Peng Jiang, Hong Liu, Yu Zhao, Zhelong Zhou, Ke Huang, Zhihai Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan 430074 Peoples R China Univ Texas Arlington Comp Sci & Engn Dept Arlington TX 76019 USA Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan 430074 Peoples R China Tencent Shenzhen Peoples R China

Reducing the byte miss ratio (BMR) in the Content Delivery Network (CDN) caches can help providers save on the cost of paying for traffic. When evicting objects or files of different sizes in the caches of CDNs, it is no longer sufficient to pursue an optimal object miss ratio (OMR) by approximating Belady to ensure an optimal BMR. Our experimental observations suggest that there are multiple request sequence windows. In these windows, a replacement policy prioritizes the eviction of objects with large sizes and ultimately evicts the object with the longest reuse distance, lowering the BMR without increasing the OMR. To accurately capture those windows, we monitor the changes in OMR and BMR using a deep reinforcement learning (RL) model and then implement a BMR-friendly replacement algorithm in these windows. Based on this policy, we propose a Belady and Size Eviction (LRU-BaSE) algorithm that reduces BMR while maintaining OMR. To make LRU-BaSE efficient and practical, we address the feedback delay problem of RL with a two-pronged approach. On the one hand, we shorten the LRU-base decision region based on the observation that the rear section of the cache queue contains most of the eviction candidates. On the other hand, the request distribution on CDNs makes it feasible to divide the learning region into multiple sub-regions that are each learned with reduced time and increased accuracy. In real CDN systems, LRU-BaSE outperforms LRU by reducing "backing to OS" traffic and access latency by 30.05% and 17.07%, respectively, on average. In simulator tests, LRU-BaSE outperforms state-of-the-art cache replacement policies. On average, LRU-BaSE's BMR is 0.63% and 0.33% less than that of Belady and Practical Flow-based Offline Optimal (PFOO), respectively. In addition, compared to Learning Relaxed Belady (LRB), LRU-BaSE can yield relatively stable performance when facing workload drift.

关键词： Byte miss ratio content delivery network rear section reinforcement learning replacement algorithm Byte miss ratio content delivery network rear section reinforcement learning replacement algorithm

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Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

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Computers, Materials & Continua 2023年第3期74卷 4951-4963页

作者： Allam Abumwais Mahmoud Obaid Computer Systems Engineering Arab American UniversityJenin240Palestine

Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)*** bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache *** main problem in improving memory performance is the shared cache architecture and cache *** paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access replacement algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core *** Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache *** show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared *** new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 *** miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 *** results could open a new window for solving the long-standing problems with shared cache in multi-core processors.

关键词： Multi-core processor shared cache content addressable memory dual port CAM replacement algorithm benchmark program

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Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits

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JOURNAL OF SUPERCOMPUTING 2019年第7期75卷 3945-3974页

作者： Ghaemi, Seyedeh Golsana Ahmadpour, Iman Ardebili, Mehdi Farbeh, Hamed SUT Tehran Iran TU Tehran Iran Amirkabir Univ Technol POB 15916-34311 Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran

Emerging non-volatile memories (NVMs) are known as promising alternatives to SRAMs in on-chip caches. However, their limited write endurance is a major challenge when NVMs are employed in these highly frequently written caches. Early wear-out of NVM cells makes the lifetime of the caches extremely insufficient for nowadays computational systems. Previous studies only addressed the lifetime of data part in the cache. This paper first demonstrates that the age bits field of the cache replacement algorithm is the most frequently written part of a cache block and its lifetime is shorter than that of data part by more than 27x. Second, it investigates the effect of age bits wear-out on the cache operation and shows that the performance is severely degraded after even a small portion of age bits become non-operational. Third, a novel cache replacement algorithm, so-called Sleepy-LRU, is proposed to reduce the write activity of the age bits with negligible overheads. The evaluations show that Sleepy-LRU extends the lifetime of instruction and data caches to 3.63x and 3.00x, respectively, with an average of 0.06% performance overhead. In addition, Sleepy-LRU imposes no area and power consumption overhead.

关键词： Age bits Lifetime Non-volatile caches replacement algorithm Write endurance

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Reducing outgoing traffic of proxy cache by using client-cluster

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JOURNAL OF COMMUNICATIONS AND NETWORKS 2006年第3期8卷 330-338页

作者： Kim, Kyungbaek Park, Daeyeon Korea Adv Inst Sci & Technol Div Elect Engn Dept Elect Engn & Comp Sci Taejon 305701 South Korea

Many web cache systems and policies concerning them have been proposed. These studies, however, consider large objects less useful than small objects in terms of performance, and evict them as soon as possible. Even if this approach increases the hit rate, the byte hit rate decreases and the connections occurring over congested links to outside networks waste more bandwidth in obtaining large objects. This paper puts forth a client-cluster approach for improving the web cache system. The client-cluster is composed of the residual resources of clients and utilizes them as exclusive storage for large objects. This proposed system achieves not only a high hit rate but also a high byte hit rate, while reducing outgoing traffic. The distributed hash table (DHT) based peer-to-peer lookup protocol is utilized to manage the client-cluster. With the natural characteristics of this protocol, the proposed system with the client-cluster is self-organizing, fault-tolerant, well-balanced, and scalable. Additionally, the large objects are managed with an index based allocation method, which balances the loads of all clients well. The performance of the cache system is examined via a trace driven simulation and an effective enhancement of the proxy cache performance is demonstrated.

关键词： client-cluster peer-to-peer replacement algorithm web caching

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PERFORMANCE ANALYSES OF PAGING-algorithmS FOR COMPILATION OF A HIGHLY MODULARIZED PROGRAM

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 1981年第2期7卷 248-254页

作者： CHUSHO, T HAYASHI, T HITACHI LTD OMIKA WORKSIBARAKIJAPAN

Previous work on paging behavior has concentrated on procedures rather than data. Recent research: 1. clarifies the paging behavior of data referenced by a newly developed language processor, and 2. analyzes theoretically the performance of several page replacement algorithms with no loss of generality. Experimental analyses demonstrate that the optimum page size for these data is small and locality is evident (but not so high in comparison with that for procedures), and that the efficiency of each replacement algorithm can be ranked in descending order as LRU, simplified LRUs, and first-in-first-out (FIFO). The language processor is improved on the basis of these results. Assuming the existence of locality, the performance of algorithms is analyzed theoretically. Difference in performance between LRU and FIFO is evaluated by upper and lower bound functions and is found to increase at low fault rate. The reason for the difference between LRU and simplified LRUs is analyzed by the period measure for which information about recent references to pages is collected. It is concluded that the performance of simplified LRUs is consistent with this measure and strongly depends on the reset timing of LRU-flags. Figures.

关键词： replacement algorithm Compilation Fault Rate Locality LRU Modular Programming Optimum Page Size Paging Behavior Of Data Relative Difference In Performance

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Bias of group generators in the solvable case

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ISRAEL JOURNAL OF MATHEMATICS 2015年第2期207卷 739-761页

作者： Crestani, Eleonora Lucchini, Andrea Dipartimento Matemat I-35121 Padua Italy

Babai and Pak demonstrated a weakness in the product replacement algorithm, a widely used heuristic algorithm intended to rapidly generate nearly uniformly distributed random elements in a finite group G. It was an open question whether the same weakness can be exhibited if one considers only finite solvable groups. We give an affirmative solution to this problem. We consider the distribution of the first component in a k-tuple chosen uniformly in the set of all the k-tuples generating G and construct an infinite sequence of finite solvable groups G for which this distribution turns out to be very far from uniform.

关键词： Finite Statistical Biases bias(electronics) Bias Heuristic algorithms Soluble Hypodynamia Bias replacement algorithm

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